參數(shù)資料
型號(hào): ISP1161A1
廠商: NXP Semiconductors N.V.
英文描述: Universal Serial Bus single-chip host and device controller
中文描述: 通用串行總線的單芯片主機(jī)和設(shè)備控制器
文件頁數(shù): 17/127頁
文件大?。?/td> 2762K
代理商: ISP1161A1
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
17 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
8.4 Microprocessor read/write ISP1161’s internal FIFO buffer RAM by
PIO mode
Since ISP1161’s internal memory is structured as a FIFO buffer RAM, the FIFO buffer
RAM is mapped to dedicated register fields. Therefore, accessing ISP1161’s internal
FIFO buffer RAM is just like accessing the internal control registers in multiple data
phases.
Figure 17
shows a complete access cycle of ISP1161’s internal FIFO buffer RAM. For
a write cycle, the microprocessor first writes the FIFO buffer RAM’s command code to
the command port, and then writes the data words one by one to the data port until
half of the transfer’s byte count is reached. The HcTransferCounter register (22H -
Read, A2H - Write) is used to specify the byte count of a FIFO buffer RAM’s read
cycle or write cycle. Every access cycle must be in the same access direction. The
read cycle procedure is similar to the write cycle.
For ISP1161 DC’s FIFO buffer RAM access, see
Section 11
.
8.5 Microprocessor read/write ISP1161’s internal FIFO buffer RAM by
DMA mode
The DMA interface between a microprocessor and ISP1161 is shown in
Figure 10
.
When doing a DMA transfer, at the beginning of every burst the ISP1161 outputs a
DMA request to the microprocessor via the DREQ pin (DREQ1 for HC, DREQ2 for
DC). After receiving this signal, the microprocessor will reply with a DMA
acknowledge to ISP1161 via the DACK pin (DACK1 for HC, DACK2 for DC), and at
the same time, do the DMA transfer through the data bus. For normal DMA mode, the
Fig 16. Accessing ISP1161 DC control registers.
Signals
Valid status
0
11
CS
A1, A0
Valid status
0
10
Valid status
0
10
RD = 1,
WR = 0
data bus
Command code
Register data
(upper word)
Register data
(lower word)
MGT940
RD, WR
RD = 0 (read) or
WR = 0 (write)
RD = 0 (read) or
WR = 0 (write)
Fig 17. ISP1161’s internal FIFO buffer RAM access cycle.
MGT941
read/write data
#1 (16 bits)
FIFO buffer RAM access cycle (transfer counter = 2N)
t
read/write data
#2 (16 bits)
read/write data
#N (16 bits)
write command
(16 bits)
相關(guān)PDF資料
PDF描述
ISP1161A1BD Universal Serial Bus single-chip host and device controller
ISP1161A1BM Universal Serial Bus single-chip host and device controller
ISP1161BD Full-speed Universal Serial Bus single-chip host and device controller
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