參數(shù)資料
型號: ISP1161A1
廠商: NXP Semiconductors N.V.
英文描述: Universal Serial Bus single-chip host and device controller
中文描述: 通用串行總線的單芯片主機和設(shè)備控制器
文件頁數(shù): 61/127頁
文件大小: 2762K
代理商: ISP1161A1
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
61 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
13.1.6
HcInterruptDisable Register
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Thus, writing a logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
writing a logic 0 to a bit in this register leaves the corresponding bit in the
HcInterruptEnable register unchanged. On a read, the current value of the
HcInterruptEnable register is returned.
Table 26: HcInterruptDisable Register: bit allocation
Bit
31
Symbol
MIE
Reset
0
Access
Bit
23
Symbol
Reset
Access
Bit
15
Symbol
Reset
Access
Bit
7
Symbol
reserved
Reset
0
Access
30
29
28
27
26
25
24
reserved
0
0
0
0
0
0
0
R/W
22
21
20
19
18
17
16
reserved
00H
R/W
14
13
12
11
10
9
8
reserved
00H
R/W
6
5
4
3
2
1
0
RHSC
0
FNO
0
UE
0
RD
0
SF
0
reserved
0
SO
0
R/W
Table 27: HcInterruptDisable Register: bit description
Bit
Symbol
Description
31
MIE
A logic 0 is ignored by the HC. A logic 1 disables interrupt
generation due to events specified in other bits of this register. This
field is set after a hardware or software reset.
30 to 8
-
reserved
7
-
reserved
6
RHSC
0 —
ignore
1 —
disable interrupt generation due to Root Hub Status Change
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