參數(shù)資料
型號(hào): IDT82P5088BBG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 6/81頁(yè)
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 OCTAL 256PBGA
標(biāo)準(zhǔn)包裝: 90
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 8
電源電壓: 1.8V, 3.3V
功率(瓦特): 2.57W
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 托盤(pán)
包括: 集成式時(shí)鐘適配器
IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
PIN DESCRIPTION
14
February 5, 2009
DS / RD / SCLK
Input
N10
DS: Data Strobe (Active Low)
In parallel Motorola mode, this pin is active low.
RD: Read Strobe (Active Low)
In parallel Intel mode, this pin is active low for read operation.
SCLK: Serial Clock
In SPI mode, this pin inputs the timing for the SDO and SDI pins. The signal on the SDO pin is updated on the falling
edge of SCLK, while the signal on the SDI pin is sampled on the rising edge of SCLK.
DS / RD / SCLK is a Schmitt-trigger input.
SPIEN
Input
N11
SPIEN: Serial Microprocessor Interface Enable
When this pin is low, the microprocessor interface is in parallel mode.
When this pin is high, the microprocessor interface is in SPI mode.
SPIEN is a Schmitt-trigger input.
JTAG Signals
TRST
Input
R13
TRST: Test Reset (Active Low)
A low signal on this pin resets the JTAG test port. This pin is a Schmitt-triggered input with an internal pull-up resistor.
It must be connected to the RESET pin or ground when JTAG is not used.
TMS
Input
T14
TMS: Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge of TCK. This pin is a
Schmitt-triggered input with an internal pull-up resistor.
TCK
Input
T15
TCK: Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge of TCK and TDO is
clocked out of the device on the falling edge of TCK. This pin is a Schmitt-triggered input with an internal pull-up
resistor.
TDI
Input
T13
TDI: Test Input
The test data is sampled at this pin on the rising edge of TCK. This pin is a Schmitt-triggered input with an internal
pull-up resistor.
TDO
High-Z
R14
TDO: Test Output
The test data are output on this pin. It is updated on the falling edge of TCK. This pin is High-Z except during the pro-
cess of data scanning.
Power Supplies and Grounds
VDDDIO
Power
F5, G5,
H5, J5,
J12, K5,
K12, L12,
M12, R12
VDDDIO: 3.3 V I/O Power Supply
VDDDC
Power
H6, H7,
H8, J6,
J7, J8,
J9, J10,
J11, K6, K7,
K8, K9,
K10,
K11,
L6, L7,
L8, L9,
L10,
L11
VDDDC: 1.8 V Digital Core Power Supply
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
PBGA256
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