參數(shù)資料
型號： IDT82P5088BBG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 20/81頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 OCTAL 256PBGA
標(biāo)準(zhǔn)包裝： 90
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 8
電源電壓： 1.8V, 3.3V
功率（瓦特）： 2.57W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 托盤
包括： 集成式時鐘適配器
IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
FUNCTIONAL DESCRIPTION
27
February 5, 2009
RJA_IS bit (INTS1, 3BH...). When the RJA_IS bit is ‘1’, an interrupt will
be reported on the INT pin if enabled by the RJA_IE bit (INTENC1,
34H...).
To avoid overflow or underflow, the JA-Limit function can be enabled
by setting the RJA_LIMT bit (RJACF, 27H...). When the JA-Limit func-
tion is enabled, the speed of the outgoing data will be adjusted automat-
ically if the FIFO is close to its full or emptiness. The criteria of speed
adjustment start are listed in Table 17. Though the JA-Limit function can
reduce the possibility of FIFO overflow and underflow, the quality of jitter
attenuation is deteriorated.
Selected by the RJITT_TEST bit (RJACF, 27H...), the real time
interval between the read and write pointer of the FIFO or the peak-peak
interval between the read and write pointer of the FIFO can be indicated
in the RJITT[6:0] bits (RJITT, 39H...). When the RJITT_TEST bit is ‘0’,
the current interval between the read and write pointer of the FIFO will
be written into the RJITT[6:0] bits. When the RJITT_TEST bit is ‘1’, the
current interval will be compared with the old one in the RJITT[6:0] bits
and the larger one will be indicated by the RJITT[6:0] bits.
The performance of Receive Jitter Attenuator meets the ITU-T I.431,
G.703, G.736 - 739, G.823, G.824, ETSI 300011, ETSI TBR 12/13,
AT&T TR62411, TR43802, TR-TSY 009, TR-TSY 253, TR-TRY 499
Transfer for details.
3.3.12 LOS AND AIS DETECTION
3.3.12.1LOS DETECTION
The Loss of Signal Detector monitors the amplitude of the incoming sig-
nal level and pulse density of the received signal on RTIPn and RRINGn.
LOS declare (LOS=1)
A LOS is detected when the incoming signal has “no transitions”, i.e.,
when the signal level is less than Q dB below nominal for N consecutive
pulse intervals. Here N is defined by LAC bit (MAINT1, 2CH...). LOS will be
declared by pulling LOSn pin to high(LOS=1) and LOS interrupt will be gen-
erated if it is not masked.
LOS clear (LOS=0)
The LOS is cleared when the incoming signal has “transitions”, i.e.,
when the signal level is greater than P dB below nominal and has an aver-
age pulse density of at least 12.5% for M consecutive pulse intervals, start-
ing with the receipt of a pulse. Here M is defined by LAC bit (MAINT1,
2CH...). LOS status is cleared by pulling LOSn pin to low.
Figure-13 LOS Declare and Clear
LOS detect level threshold
In short haul mode, the amplitude threshold Q is fixed on 800 mVpp,
while P=Q+200 mVpp (200 mVpp is the LOS level detect hysteresis). In line
monitor mode, the amplitude threshold Q is fixed on 1600 mVpp, while
P=Q+400 mVpp (400 mVpp is the LOS level detect hysteresis).
In long haul mode, the value of Q can be selected by LOS[4:0] bit
(RCF1, 29H...), while P=Q+4 dB (4 dB is the LOS level detect hysteresis).
The LOS[4:0] default value is 10101 (-46 dB).
Criteria for declare and clear of a LOS detect
The detection supports the ANSI T1.231 and I.431 for T1/J1 mode and
G.775 and ETSI 300233/I.431 for E1 mode. The criteria can be selected
by LAC bit (MAINT1, 2CH...) and TE_MODE bit (T1E1 mode, 20H...).
Table-19 and Table-20 summarize LOS declare and clear criteria for
both short haul and long haul application.
All Ones output during LOS
On the system side, the RDPn/RDNn will reflect the input pulse “transi-
tion” at the RTIPn/RRINGn side and output recovery clock (but the quality
of the output clock can not be guaranteed when the input level is lower than
Table-17 Criteria Of Speed Adjustment Start
FIFO Depth
Criteria Of Speed Adjustment Start
32 bits
2-bit close to full or empty
64 bits
3-bit close to full or empty
128 bits
4-bit close to full or empty
Table-18 Related Bit / Register In Chapter 3.3.11
Bit
Register
Address (Hex)
RJA_E
Receive Jitter Attenuation Configura-
tion
X27H
RJA_DP[1:0]
RJA_BW
RJA_LIMT
RJITT_TEST
RJA_IS
Interrupt Status 1
X3BH
RJA_IE
Interrupt Enable Control 1
X34H
RJITT[6:0]
Receive Jitter Measure Value Indication
X39H
signal level<Q
(observing windows= N)
(observing windows= M)
signal level>P
density=OK
LOS=1
LOS=0
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參數(shù)描述
IDT82P5088BBG8 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 OCTAL 256PBGA
IDT82V1054A 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
IDT82V1054APF 功能描述:IC PCM CODEC 4CH MPI 3.3V 64TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
IDT82V1054APF8 功能描述:IC PCM CODEC 4CH MPI 3.3V 64TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
IDT82V1054APFG 功能描述:IC PCM CODEC 4CH MPI 3.3V 64TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
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