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參數(shù)資料
| 型號： | IDT82P5088BBG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/81頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 OCTAL 256PBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 功能： | 線路接口單元（LIU） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 8 |
| 電源電壓： | 1.8V, 3.3V |
| 功率（瓦特）： | 2.57W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（17x17） |
| 包裝： | 托盤 |
| 包括： | 集成式時鐘適配器 |
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IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
PIN DESCRIPTION
12
February 5, 2009
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
LOS8
Output
R6
N6
T5
P5
M5
R4
N4
R3
LOSn: Loss of Signal Output for Channel 1~8
These pins are used to indicate the loss of received signals. When LOSn pin becomes high, it indicates the loss of
received signals in channel n. The LOSn pin will become low automatically when valid received signal is detected
again. The criteria of loss of signal are described in 3.3.12 LOS AND AIS DETECTION.
Clock Generator
OSCI
Input
B13
OSCI: Crystal Oscillator Input
This pin is connected to an external clock source.
The clock frequency of OSCI is defined by CLK_SEL[2:0]. The clock accuracy should be ±32 ppm and duty cycle
should be from 40% to 60%.
OSCO
Output
C13
OSCO: Crystal Oscillator Output
This pin outputs the inverted, buffered clock input from OSCI.
CLK_SEL[0]
CLK_SEL[1]
CLK_SEL[2]
Input
D15
C14
B15
CLK_SEL[2:0]: Clock Selection
These three pins select the input clock signal:
When the CLK_SEL[2] pin is low, the input clock signal is N X 1.544 MHz;
When the CLK_SEL[2] pin is high, the input clock signal is N X 2.048 MHz.
When the CLK_SEL[1:0] pins are ‘00’, the N is 1;
When the CLK_SEL[1:0] pins are ‘01’, the N is 2;
When the CLK_SEL[1:0] pins are ‘10’, the N is 3;
When the CLK_SEL[1:0] pins are ‘11’, the N is 4.
CLK_SEL[2:0] are Schmitt-trigger inputs.
CLK_GEN_1.54
4
Output
A16
CLK_GEN_1.544: Clock Generator 1.544 MHz Output
This pin outputs the 1.544 MHz clock signal generated by the Clock Generator.
CLK_GEN_2.04
8
Output
D14
CLK_GEN_2.048: Clock Generator 2.048 MHz Output
This pin outputs the 2.048 MHz clock signal generated by the Clock Generator.
REFA_OUT
Output
A15
REFA_OUT: Reference Clock Output A
The frequecy is 2.048 MHz (E1) or 1.544 MHz (T1/J1)
When no LOS is detected, this pin outputs a recovered clock from the Clock and Data Recovery function block of one
of the eight links. The link is selected by the RO1[2:0] bits (REFOUT, 07H).
When LOS is detected, this pin outputs MCLK or high level, as selected by the REFH_LOS bit (REFC, 3EH...).
Note: MCLK is a clock derived from OSCI using an internal PLL, and the frequency is 2.048 MHz (E1) or 1.544 MHz
(T1/J1).
REFB_OUT
Output
B14
REFB_OUT: Reference Clock Output B
The frequecy is 2.048 MHz (E1) or 1.544 MHz (T1/J1)
When no LOS is detected, this pin outputs a recovered clock from the Clock and Data Recovery function block of one
of the eight links. The link is selected by the RO2[2:0] bits (REFOUT, 07H).
When LOS is detected, this pin outputs MCLK or high level, as selected by the REFH_LOS bit (REFC, 3EH...).
Control Interface
RESET
Input
A14
RESET: Reset (Active Low)
A low pulse for more than 100 ns on this pin resets the device. All the registers are accessible 2 ms after the reset.
The RESET pin is a Schmitt-trigger input with a weak pull-up resistor. The OSCI clock must exist when the device is
reset.
GPIO0
GPIO1
Output /
Input
E13
D13
General Purpose I/O [1:0]
These two pins can be defined as input pins or output pins by the DIR[1:0] bits (GPIO, 06H) respectively. When the
pins are input, their polarities are indicated by the LEVEL[1:0] bits (GPIO, 06H) respectively. When the pins are out-
put, their polarities are controlled by the LEVEL[1:0] bits (GPIO, 06H) respectively.
GPIO[1:0] are Schmitt-trigger input/output with a pull-up resistor.
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
PBGA256
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P5088BBG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 OCTAL 256PBGA |
| IDT82V1054A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE |
| IDT82V1054APF | 功能描述:IC PCM CODEC 4CH MPI 3.3V 64TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| IDT82V1054APF8 | 功能描述:IC PCM CODEC 4CH MPI 3.3V 64TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| IDT82V1054APFG | 功能描述:IC PCM CODEC 4CH MPI 3.3V 64TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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