參數(shù)資料
型號(hào)： IDT82P5088BBG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 19/81頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 OCTAL 256PBGA
標(biāo)準(zhǔn)包裝： 90
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 8
電源電壓： 1.8V, 3.3V
功率（瓦特）： 2.57W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 托盤
包括： 集成式時(shí)鐘適配器
IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
FUNCTIONAL DESCRIPTION
26
February 5, 2009
3.3.10 G.772 NON-INTRUSIVE MONITORING
In applications using only seven channels, channel 1 can be configured
tomonitorthedatareceivedortransmittedinanyoneoftheremainingchan-
nels. The MON[3:0] bits (MON, 05H) determine which channel and which
direction (transmit/receive) will be monitored. The monitoring is non-intru-
sive per ITU-T G.772. Figure-12 illustrates the concept.
The monitored line signal (transmit or receive) goes through Channel
1's Clock and Data Recovery. The signal can be observed digitally at the
RCLK1, RD1/RDP1 and RDN1. If Channel 1 is configured to Remote Loop-
back while in the Monitoring mode, the monitored data will be output on
TTIP1/TRING1.
Figure-12 G.772 Monitoring Diagram
3.3.11 RECEIVE JITTER ATTENUATOR
The Receive Jitter Attenuator of each link can be chosen to be used
or not. This selection is made by the RJA_E bit (RJACF, 27H...).
The Jitter Attenuator consists of a FIFO and a DPLL, as shown in
The FIFO is used as a pool to buffer the jittered input data, then the
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the RJA_DP[1:0]
bits (RJACF, 27H...). Accordingly, the constant delay produced by the
Jitter Attenuator is 16 bits, 32 bits or 64 bits. The 128-bit FIFO is used
when large jitter tolerance is expected, while the 32-bit FIFO is used in
delay sensitive applications.
The DPLL is used to generate a de-jittered clock to clock out the data
stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF). The jitter whose
frequency is lower than the CF passes through the DPLL without any
attenuation. In T1/J1 applications, the CF of the DPLL can be 5 Hz or
1.26 Hz, as selected by the RJA_BW bit. In E1 applications, the CF of
the DPLL can be 6.77 Hz or 0.87 Hz, as selected by the RJA_BW bit
(RJACF, 27H...). The lower the CF is, the longer time is needed to
achieve synchronization.
If the incoming data moves faster than the outgoing data, the FIFO
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow or underflow is captured by the
Channel N (N > 2)
B8ZS/
HDB3/AMI
Encoder
Jitter
Attenuator
Line
Driver
Waveform
Shaper/LBO
B8ZS/
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
LOS/AIS
Detector
Clock and
Data
Recovery
Transmitter
Internal
Termination
Receiver
Internal
Termination
TCLKn
TDNn
TDn/TDPn
RCLKn
CVn/RDNn
LOSn
RDn/RDPn
RRINGn
TTIPn
TRINGn
RTIPn
Channel 1
B8ZS/
HDB3/AMI
Encoder
Jitter
Attenuator
Line
Driver
Waveform
Shaper/LBO
B8ZS/
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
LOS/AIS
Detector
Clock and
Data
Recovery
Transmitter
Internal
Termination
Receiver
Internal
Termination
TCLK1
TDN1
TDn/TDP1
RCLK1
CVn/RDN1
LOS1
RDn/RDP1
RRING1
TTIP1
TRING1
RTIP1
Remote
Loopback
G.772
Monitor
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