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參數(shù)資料
| 型號： | IDT82P5088BBG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 24/81頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 OCTAL 256PBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 功能： | 線路接口單元（LIU） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 8 |
| 電源電壓： | 1.8V, 3.3V |
| 功率（瓦特）： | 2.57W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（17x17） |
| 包裝： | 托盤 |
| 包括： | 集成式時鐘適配器 |
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IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
FUNCTIONAL DESCRIPTION
30
February 5, 2009
3.4
TRANSMIT AND DETECT INTERNAL PATTERNS
The internal patterns (All Ones, All Zeros, PRBS/QRSS pattern and
Activate/Deactivate Loopback Code) will be generated and detected by the
IDT82P5088. TCLKn is used as the reference clock by default. MCLK can
also be used as the reference clock by setting the PATT_CLK bit (MAINT1,
2CH...) to ‘1’.
If the PATT_CLK bit (MAINT1, 2CH...) is set to ‘0’ and the PATT[1:0] bits
(MAINT1, 2CH...) are set to ‘00’, the transmit path will operate in normal
mode.
3.4.1
TRANSMIT ALL ONES
In transmit direction, the All Ones data can be inserted into the data
stream when the PATT[1:0] bits (MAINT1, 2CH...) are set to ‘01’. The trans-
mit data stream is output from TTIPn/TRINGn. In this case, either TCLKn
or MCLK can be used as the transmit clock, as selected by the PATT_CLK
bit (MAINT1, 2CH...).
3.4.2
TRANSMIT ALL ZEROS
If the PATT_CLK bit (MAINT1, 2CH...) is set to ‘1’, the All Zeros will be
inserted into the transmit data stream when the PATT[1:0] bits (MAINT1,
2CH...) are set to ‘00’.
3.4.3
PRBS/QRSS GENERATION AND DETECTION
A PRBS/QRSS will be generated in the transmit direction and detected
in the receive direction by IDT82P5088. The QRSS is 220-1 for T1/J1 appli-
cations and the PRBS is 215-1 for E1 applications, with maximum zero
restrictions according to the AT&T TR62411 and ITU-T O.151.
When the PATT[1:0] bits (MAINT1, 2CH...) are set to ‘10’, the PRBS/
QRSS pattern will be inserted into the transmit data stream with the MSB
first. The PRBS/QRSS pattern will be transmitted directly or invertedly.
The PRBS/QRSS in the received data stream will be monitored. If the
PRBS/QRSS has reached synchronization status, the PRBS_S bit
(STAT0, 36H...) will be set to ‘1’, even in the presence of a logic error rate
less than or equal to 10-1. The criteria for setting/clearing the PRBS_S bit
are shown in Table-22.
PRBS data canbe inverted throughsetting the PRBS_INVbit(MAINT1,
2CH...).
Any change of PRBS_S bit will be captured by PRBS_IS bit (INTS0,
3AH...). The PRBS_IES bit (INTES, 35H...) can be used to determine
whetherthe ‘0’ to‘1’changeof PRBS_Sbitwill becapturedby thePRBS_IS
bitoranychangesofPRBS_SbitwillbecapturedbythePRBS_ISbit.When
the PRBS_IS bit is ‘1’, an interrupt will be generated if the PRBS_IE bit
(INTENC0, 33H...) is set to ‘1’.
The received PRBS/QRSS logic errors can be counted in a 16-bit
counter if the ERR_SEL [1:0] bits (MAINT6, 31H...) are set to ‘00’. Refer to
Refer to 3.6 ERROR DETECTION/COUNTING AND INSERTION for the
operation of the error counter.
Table-21 AIS Condition
ITU G.775 for E1
(LAC bit is set to ‘0’ by default)
ETSI 300233 for E1
(LAC bit is set to ‘1’)
ANSI T1.231 for T1/J1
AIS
detected
Less than 3 zeros contained in each of two consecutive
512-bit streams are received
Less than 3 zeros contained in a 512-bit
stream are received
Less than 9 zeros contained in an 8192-bit stream
(a ones density of 99.9% over a period of 5.3ms)
AIS
cleared
3 or more zeros contained in each of two consecutive
512-bit streams are received
3 or more zeros contained in a 512-bit
stream are received
9 or more zeros contained in an 8192-bit stream
are received
Table-22 Criteria for Setting/Clearing the PRBS_S Bit
PRBS/QRSS
Detection
6 or less than 6 bit errors detected in a 64 bits hopping window.
PRBS/QRSS
Missing
More than 6 bit errors detected in a 64 bits hopping window.
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相關(guān)代理商/技術(shù)參數(shù) |
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| IDT82P5088BBG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 OCTAL 256PBGA |
| IDT82V1054A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE |
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| IDT82V1054APF8 | 功能描述:IC PCM CODEC 4CH MPI 3.3V 64TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| IDT82V1054APFG | 功能描述:IC PCM CODEC 4CH MPI 3.3V 64TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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