- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384480 > ID82C284 (Intersil Corporation) Clock Generator and Ready Interface for 80C286 Processors PDF資料下載
參數(shù)資料
| 型號(hào)： | ID82C284 |
| 廠商： | Intersil Corporation |
| 英文描述： | Clock Generator and Ready Interface for 80C286 Processors |
| 中文描述： | 時(shí)鐘發(fā)生器和Ready接口80C286處理器 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 72K |
| 代理商： | ID82C284 |
5
LOW to HIGH input transition voltage. As long as the slope of
the RES input voltage remains in the same direction (increas-
ing or decreasing) around the RES input transition voltage, the
RESET output will make a single transition.
Ready Operation
The 82C284 accepts two ready sources for the system ready
signal which terminates the current bus cycle. Either a synchro-
nous (SRDY) or asynchronous ready (ARDY) source may be
used. Each ready input has an enable (SRDYEN and
ARDYEN) for selecting the type of ready source required to ter-
minate the current bus cycle. An address decoder would nor-
mally select one of the enable inputs.
READY is enabled (LOW), if either SRDY + SRDYEN = 0 or
ARDY + ARDYEN = 0 when sampled by the 82C284 READY
generation logic. READY will remain active for at least two CLK
cycles.
The READY output has an open-drain driver allowing other
ready circuits to be wired with it, as shown in Figure 4. The
READY signal of an 80C286 system requires an external
pull-up resistor. To force the READY signal inactive (HIGH)
at the start of a bus cycle, the READY output floats when
either S1 or S0 are sampled LOW at the falling edge of CLK.
Two system clock periods are allowed for the pull-up resistor
to pull the READY signal to V
lH
. When RESET is active,
READY is forced active one CLK later (see Waveforms).
Figure 5 illustrates the operation of SRDY and SRDYEN.
These inputs are sampled on the falling edge of CLK when
S1 and S0 are inactive and PCLK is HIGH. READY is forced
active when both SRDY and SRDYEN are sampled as LOW.
Figure 6 shows the operation of ARDY and ARDYEN These
inputs are sampled by an internal synchronizer at each fall-
ing edge of CLK. The output of the synchronizer is then sam-
pled when PCLK is HIGH. If the synchronizer resolved both
the ARDY and ARDYEN as active, the SRDY and SRDYEN
inputs are ignored. Either ARDY or ARDYEN must be HIGH
at the end of T
S
, therefore, at least one wait state is required
when using the ARDY and ARDYEN inputs as a basis for
generating READY.
READY remains active until either S1 or S0 are sampled
LOW, or the ready inputs are sampled as inactive.
1N914
10k
V
CC
FIGURE 3. TYPICAL RC RES TIMING CIRCUIT
10
μ
F
11
82C284
RES
+
47
C1
7
8
X1
X2
F/C
82C284
CLK
READY
V
CC
CLK
80C286
CPU OR
SUPPORT
COMPONENT
READY
6
10
4
18
V
CC
DECOUPLING
CAPACITOR
FIGURE 4. RECOMMENDED CRYSTAL AND READY
CONDITIONS
V
CC
82C284
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ID82C82 | CMOS Octal Latching Bus Driver |
| ID82C83H | CMOS Octal Latching Inverting Bus Driver |
| ID82C84A | RES,CHIP 1/8W 5% 33 OHM |
| ID82C85 | CMOS Static Clock Controller/Generator |
| ID82C86H | CMOS Octal Bus Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ID82C284-10 | 制造商:Harris Corporation 功能描述: 制造商:Intersil Corporation 功能描述: |
| ID82C284-12 | 制造商:Rochester Electronics LLC 功能描述:PERIPH CLK GENERATOR 5V 12.5MHZ 18CDIP IND - Bulk |
| ID82C37A | 制造商:HARRIS 制造商全稱:HARRIS 功能描述:CMOS High Performance Programmable DMA Controller |
| ID82C37A-12 | 制造商:HARRIS 制造商全稱:HARRIS 功能描述:CMOS High Performance Programmable DMA Controller |
| ID82C37A-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。