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參數(shù)資料
| 型號： | ID82C284 |
| 廠商： | Intersil Corporation |
| 英文描述： | Clock Generator and Ready Interface for 80C286 Processors |
| 中文描述： | 時(shí)鐘發(fā)生器和Ready接口80C286處理器 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 72K |
| 代理商： | ID82C284 |
2
Pin Description
The following pin function descriptions are for the 82C284 clock generator.
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
CLK
10
O
SYSTEM CLOCK: the signal used by the processor and support devices which must be synchro-
nous with the processor. The frequency of the CLK output has twice the desired internal processor
clock frequency. CLK can drive both TTL and CMOS level inputs.
F/C
6
I
FREQUENCY/CRYSTAL SELECT: this pin selects the source for the CLK output. When there is a
LOW level on this input, the internal crystal oscillator drives CLK. When there is a HIGH level on F/C,
the EFI input drives the CLK input. This pin can be dynamically switched, which allows changing the
processor CLK frequency while running for low-power operation, etc.
X1, X2
7, 8
I
CRYSTAL IN: the pin stop which parallel resonant, fundamental mode crystal is attached for the in-
ternal oscillator. When F/C is LOW, the internal oscillator will drive the CLK output at the crystal fre-
quency. The crystal frequency must be twice the desired internal processor clock frequency.
EFI
5
I
EXTERNAL FREQUENCY IN: drives CLK when the F/C input is HIGH. The EFI input frequency
must be twice the desired internal processor clock frequency.
PCLK
13
O
PERIPHERAL CLOCK: the output which provides a 50% duty cycle clock with one-half the frequen-
cy of CLK. PCLK will be in phase with the internal processor clock following the first bus cycle after
the processor has been reset.
ARDYEN
17
I
ASYNCHRONOUS READY ENABLE: an active LOW input which qualifies the ARDY input.
ARDYEN selects ARDY as the source of READY for the current bus cycle. Inputs to ARDYEN may
be applied asynchronously to CLK. Setup and hold times are given to assure a guaranteed response
to synchronous outputs.
ARDY
1
I
ASYNCHRONOUS READY: an active LOW input used to terminate the current bus cycle. TheARDY
input is qualified by ARDYEN. Inputs to ARDY may be applied asynchronously to CLK. Setup and
hold times are given to assure a guaranteed response to synchronous outputs.
SRDYEN
3
I
SYNCHRONOUS READY ENABLE: an active LOW input which qualifies SRDY. SRDYEN selects
SRDY as the source for READY to the CPU for the current bus cycle. Setup and hold time must be
satisfied for proper operation.
SRDY
2
I
SYNCHRONOUS READY: an active LOW input used to terminate the current bus cycle. The SRDY
input is qualified by the SRDYEN input. Setup and hold time must be satisfied for proper operation.
READY
4
O
READY: an active LOW output which signals to the processor that the current bus cycle is to be com-
pleted. The SRDY SRDYEN, ARDY, ARDYEN, S1, S0, and RES inputs control READY as explained
later in the READY generator section. READY is an open drain output requiring an external pull-up
resistor.
S0, S1
15,16
I
STATUS: these inputs prepare the 82C284 for a subsequent bus cycle. S0 and S1 synchronize
PCLK to the internal processor clock and control READY. Setup and hold times must be satisfied for
proper operation
RESET
12
O
RESET: an active HIGH output which is derived from the RES input RESET is used to force the sys-
tem into an initial state. When RESET is active, READY will be active (LOW).
RES
11
I
RESET IN: an active LOW input which generates the system reset signal (RESET). Signals to RES
may be applied asynchronously to CLK. A Schmitt trigger input is provided on RES, so that an RC
circuit can be used to provide a time delay. Setup and hold times are given to assure a guaranteed
response to synchronous inputs.
V
CC
18
SYSTEM POWER: The +5V Power Supply Pin. A 0.1
μ
F capacitor between V
CC
and GND is recom-
mended for decoupling.
GND
9
SYSTEM GROUND: 0V
82C284
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