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參數(shù)資料
| 型號： | HY5V52EMP-H |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 SYNCHRONOUS DRAM, 5.4 ns, PBGA90 |
| 封裝： | 8 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, FBGA-90 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 172K |
| 代理商： | HY5V52EMP-H |
Rev. 1.0 / Nov. 2005
11
1
Synchronous DRAM Memory 256Mbit (8Mx16bit *2stack)
HY5V52E(L)M(P) Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Note: 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Parameter
Symbol
6
H
Unit
Note
Min
Max
Min
Max
System ClockCycle Time
CL = 3
tCK3
6.0
1000
7.5
1000
ns
CL = 2
tCK2
10.0
ns
Clock High Pulse Width
tCHW
2.0
-
2.5
-
ns
1
Clock Low Pulse Width
tCLW
2.0
-
2.5
-
ns
1
Access Time From Clock
CL = 3
tAC3
-5.4
ns
2
CL = 2
tAC2
-6.0
ns
Data-out Hold Time
tOH
2.0
-
2.5
-
ns
Data-Input Setup Time
tDS
1.5
-
1.5
-
ns
1
Data-Input Hold Time
tDH
0.8
-
0.8
-
ns
1
Address Setup Time
tAS
1.5
-
1.5
-
ns
1
Address Hold Time
tAH
0.8
-
0.8
-
ns
1
CKE Setup Time
tCKS
1.5
-
1.5
-
ns
1
CKE Hold Time
tCKH
0.8
-
0.8
-
ns
1
Command Setup Time
tCS
1.5
-
1.5
-
ns
1
Command Hold Time
tCH
0.8
-
0.8
-
ns
1
CLK to Data Output in Low-Z Time
tOLZ
1.0
-
1.5
-
ns
CLK to Data Output in High-Z
Time
CL = 3
tOHZ3
5.4
ns
CL = 2
tOHZ2
6.0
ns
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| HY5V52F | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 32bits Synchronous DRAM |
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