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12
AMPS Mode
The AMPS chain consists of an
image reject mixer and a driver
amplifier. The image reject mixer
eliminates the requirement for an
image reject filter between the
upconverter and the amplifier,
however the output of the mixer
and the input to the amplifier are
routed externally to provide the
option of using a filter.
The AMPS upconverter consists
of two double balanced active
mixers driven by quadrature-
phased LO and IF signals. The LO
and IF phase shifters are imple-
mented on-chip.
The differential IF input to the
mixer is shared with the PCS
band, and is explained in the PCS
CDMA mode description. The
output of the double balanced
mixer is also differential and
appears across ampsMixOutM
(pin 1) and ampsMixOutP
(pin 2). As the mixer output is
open collector, these pins need an
external connection to Vcc. If
single ended operation is re-
quired, the output can be taken
from ampsMixOutM with
ampsMixOutP being biased to
Vcc and RF terminated. A resistor
can be placed across the two pins
to set the impedance of this port
to a suitable level.
With a LO power of –11 dBm and
an IF input voltage of 480 mVp-p
differential, the upconverter
delivers –7 dBm into a 50
load
with a typical image rejection of
30 dBc. At an output power of
–7 dBm, the mixer exhibits a
noise power of –145 dBm/Hz at
45 MHz carrier offset.
The AMPS driver amplifier input
is internally AC coupled with an
on chip capacitor. An external
matching circuit is required to
transform the impedance of the
input to the required external
filter impedance, which is nomi-
nally 50
. The output of the
AMPS amplifier needs to be
connected to Vcc via an external
inductor. In most applications a
simple 2 element matching
network can provide an accept-
able match to 50
. At 835 MHz
the driver produces 22 dB of gain
and an output P1dB of 8 dBm. At
11 dBm output power into a 50
load, the receive band noise is
typically –134 dBm/Hz.
Example Circuits
This section illustrates several
example circuits for the
HPMX-7201. The Figure 31 circuit
is based on the HPMX-7201 demo
board and can be used as a
starting point for designing with
the HPMX-7201. Note that the
ground pins on the part are not
shown. Proper decoupling of Vcc
and VccBat is also required.
Additional decoupling may be
required on the control lines. In
some applications RfTxAgc is
driven with a Pulse Density
Modulated (PDM) signal, in this
case, a filter (typically R-C) is
needed. See the following section
on supply voltage partitioning for
more information.
The circuit shown in Figure 32 is
an example of how to interface
the HPMX-7201 to a 50
IF
source for testing purposes. In
most applications, the IF port
impedance is set by an IF filter
with an impedance higher than
50
. This is the circuit used for
testing the HPMX-7201, and is
also present on the HPMX-7201
demo board.
PCB Layout and Supply
Decoupling
The HPMX-7201 can optionally
operate from separate regulated
and unregulated voltage supplies
to save regulator current.
To insure optimum isolation
between the separate sections of
the HPMX-7201, it is recom-
mended that decoupling capaci-
tors be used, as well as good RF
PCB layout techniques. A star
topology with each Vcc
(or VccBat) pin on the device
having a high frequency
decoupling capacitor located
close by followed by an individual
trace to a central Vcc node with
good low frequency decoupling
can be used to minimize supply
coupling. To further reduce
coupling use a separate vias to
the ground plane for each
decoupling capacitor and ground
pin, as this minimizes common
ground inductance.
System Level Diagram
In a typical application and with a
maximum input signal at the IF
input port Figure 33 shows the
expected power levels and
voltages at different points of the
HPMX-7201. These measurements
are made using a high impedance
probe to ensure minimal loading
of the circuit with the probe.
Figure 33 is also included to show
how the HPMX-7201 interfaces
with other components to form a
dual-band, dual-mode handset.