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參數(shù)資料
| 型號(hào)： | HPMX-7201 |
| 英文描述： | Upconverter(上變頻器) |
| 中文描述： | 變頻器（上變頻器） |
| 文件頁數(shù)： | 11/19頁 |
| 文件大?。?/td> | 163K |
| 代理商： | HPMX-7201 |
11
Theory of Operation
The HPMX-7201 is designed for
operation in Dual Band/Dual
mode PCS/AMPS handsets. The
device has four modes of opera-
tion set by the pins pwrDn, fm,
and cdmaOutSel as represented
in Table 1. Additionally the gain
in PCS CDMA mode is adjustable
by controlling the RfTxAgc pin.
Refer to Figure 31 for reference
on circuit descriptions.
PCS CDMA Mode
The PCS CDMA chain consists of
a double balanced active mixer, a
variable gain amplifier (VGA) and
an output switch. The output
switch connects the VGA to one
of two output pins according to
the logic level present at the
cdmaOutSel pin (pin 17). The
same VGA is used for both
outputs, so the switch is typically
used only when split band filters
are present at the output of the
HPMX-7201.
The differential IF input to the
balanced mixer ifInP and ifInM
(pins 9 and 10) have a nominal
differential impedance of 360
. If
a single ended 50
source is used
to drive these inputs, see Fig-
ure 32 for an example test circuit.
The IF and LO inputs are com-
mon to both PCS and AMPS. The
Table 1: Modes of Operation
pwrDn
0
1
1
1
*
X indicates a don’t care state
fm
X
*
0
1
1
cdmaOutSel
X
X
0
1
Mode
Power down
AMPS mode
PCS CDMA Output 2
PCS CDMA Output 1
output of the CDMA mixer is a
differential signal across
cdmaMixOutP and cdmaMixOutM
(pins 8 and 7). Both pins are
open collector and need external
connections to Vcc. See Interface
Circuits section for more informa-
tion. If single ended operation is
required the output can be taken
from cdmaMixOutP or
cdmaMixOutM with the other
output being bypassed. A resistor
can be placed across the two pins
to set the output impedance.
The HPMX-7201 PCS CDMA
upconverter mixer includes an LO
buffer which allows operation at
low LO input power and low
supply levels. With a LO input of
–11 dBm and an IF input differen-
tial signal of 480 mVp-p, the
upconverter typically delivers
–7 dBm when matched to a 50
load at 1880 MHz. The mixer
ACPR performance is
–60 dBc/30 kHz (at 1.25 MHz
offset frequency) with an output
noise power of –155 dBm/Hz at
+80 MHz offset.
The mixer output is typically
connected through an off-chip
filter and then connected to the
VGA. The input to the VGA is
single ended (cdmaDrvIn, pin 4)
and is easily matched to 50 ohms.
The VGA gain ranges from –10 to
+23 dB and is controlled via the
RfTxAgc pin (pin 15). If connec-
tion to a Pulse Density Modula-
tion signal is used, an external
filter is required to generate the
control voltage for this input.
The VGA is implemented in a 2
stage common-emitter configura-
tion which offers 33 dB (typ.) gain
control range (-10 dB to 23 dB
gain) with a linear gain (in dB) vs.
voltage transfer characteristic.
See the
Typical Performance
Graphs
for more information.
The HPMX-7201 VGA features
adaptive biasing, which decreases
the bias current to the VGA at
lower gain levels, thus decreasing
the power consumption of the
VGA, see the typical performance
graphs for more information. The
ACPR performance is also a
function of the bias current and
the linearity increases at higher
RfTxAgc voltages. When used in
association with an IF AGC
amplifier this feature allows the
required ACPR to be achieved at
the minimum possible supply
current for each targeted output
power. See the
Applications
Notes
section for more detail on
adaptive biasing and optimizing
the supply current drawn by the
HPMX-7201 in a handset.
The output of the VGA is routed
through a band switch controlled
by the cdmaOutSel pin (pin 17),
Table 2 represents the functional-
ity of this switch. This feature can
be used to drive a split band PCS
Tx filter. Split band filters are
often needed to minimize receive
band noise injected by the
transmit chain into the LNA
through the duplexer. This
technique is frequently necessary
to meet receiver sensitivity
requirements due to the closely
spaced Rx and Tx frequency
allocations used for PCS systems.
Table 2:
PCS Output Switch Operation
cdmaOutSel
Logic 1 (>2.5V)
Logic 0 (<0.5V)
Active Output
cdmaDrvOut1 (pin 22)
cdmaDrvOut2 (pin 19)
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