參數(shù)資料
型號(hào)： HM5212165F
廠商： Hitachi,Ltd.
英文描述： 128M LVTTL interface SDRAM(128M LVTTL 接口同步DRAM)
中文描述： 128M的LVTTL接口的SDRAM（128M的LVTTL接口同步的DRAM）
文件頁(yè)數(shù)： 9/63頁(yè)
文件大小： 858K
代理商： HM5212165F
HM5212165F/HM5212805F-75/A60/B60
9
Column address strobe and write command [WRIT]:
This command starts a write operation. When the
burst write mode is selected, the column address (AY0 to AY8; HM5212165F, AY0 to AY9; HM5212805F)
and the bank select address (A12/A13) become the burst write start address. When the single write mode is
selected, data is only written to the location specified by the column address (AY0 to AY8; HM5212165F,
AY0 to AY9; HM5212805F) and the bank select address (A12/A13).
Write with auto-precharge [WRIT A]:
This command automatically performs a precharge operation after a
burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page,
this command is illegal.
Row address strobe and bank activate [ACTV]:
This command activates the bank that is selected by
A12/A13 (BS) and determines the row address (AX0 to AX11). When A12 and A13 are Low, bank 0 is
activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank
2 is activated. When A12 and A13 are High, bank 3 is activated.
Precharge selected bank [PRE]:
This command starts precharge operation for the bank selected by
A12/A13. If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If
A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected.
Precharge all banks [PALL]:
This command starts a precharge operation for all banks.
Refresh [REF/SELF]:
This command starts the refresh operation. There are two types of refresh operation,
the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]:
The SDRAM has a mode register that defines how it operates. The mode register
is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the mode
register configuration. After power on, the contents of the mode register are undefined, execute the mode
register set command to set up the mode register.
相關(guān)PDF資料
PDF描述
HM5225165BTT-75 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5225805BLTT-A6 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5225405B-B6 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5225405BLTT-75 POT 20K OHM 9MM HORZ NO BUSHING
HM5225405BLTT-A6 POT 5K OHM 9MM HORZ NO BUSHING
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM5212165FLTD-75 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM
HM5212165FLTD-A60 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM
HM5212165FLTD-B60 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM
HM5212165FTD-75 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM
HM5212165FTD-A60 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM
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