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參數(shù)資料
| 型號： | HM5212165F |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 128M LVTTL interface SDRAM(128M LVTTL 接口同步DRAM) |
| 中文描述： | 128M的LVTTL接口的SDRAM（128M的LVTTL接口同步的DRAM） |
| 文件頁數(shù)： | 20/63頁 |
| 文件大?。?/td> | 858K |
| 代理商： | HM5212165F |
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HM5212165F/HM5212805F-75/A60/B60
20
Operation of the SDRAM
Read/Write Operations
Bank active:
Before executing a read or write operation, the corresponding bank and the row address must be
activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to
the status of the A12/A13 pin, and the row address (AX0 to AX11) is activated by the A0 to A11 pins at the
bank active command cycle. An interval of t
RCD
is required between the bank active command input and the
following read/write command input.
Read operation:
A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (
CAS
latency-1) cycle after read command set. HM5212165F, HM5212805F can perform a burst read
operation.
The burst length can be set to 1, 2, 4, 8 or full-page (512; HM5212165F, 1024; HM5212805F). The start
address for a burst read is specified by the column address (AY0 to AY8; HM5212165F, AY0 to AY9;
HM5212805F) and the bank select address (A12/A13) at the read command set cycle. In a read operation,
data output starts after the number of clocks specified by the
CAS
latency. The
CAS
latency can be set to 2 or
3. When the burst length is 1, 2, 4, 8, the Dout buffer automatically becomes High-Z at the next clock after
the successive burst-length data has been output. The
CAS
latency and burst length must be specified at the
mode register.
CAS
Latency
READ
CLK
Command
Dout
ACTV
Row
Column
Address
CL = 2
CL = 3
out 0
out 1
out 2
out 3
out 0
out 1
out 2
out 3
t
RCD
CL =
CAS
latency
Burst Length = 4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5225165BTT-75 | 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225805BLTT-A6 | 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225405B-B6 | 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225405BLTT-75 | POT 20K OHM 9MM HORZ NO BUSHING |
| HM5225405BLTT-A6 | POT 5K OHM 9MM HORZ NO BUSHING |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5212165FLTD-75 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
| HM5212165FLTD-A60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
| HM5212165FLTD-B60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
| HM5212165FTD-75 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
| HM5212165FTD-A60 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM |
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