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參數(shù)資料
| 型號(hào)： | HDMP-0450 |
| 英文描述： | Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops |
| 中文描述： | 四端口旁路電路的光纖通道仲裁環(huán)路 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大小： | 269K |
| 代理商： | HDMP-0450 |
9
Pin Diagram and Recommended Supply Filtering
Figure 8. HDMP-0450 package layout and marking, top view.
Figure 9. Recommended power supply filtering.
23
12 13 14 15 16 17 18 19 20 21 22
GND
V
CC
GND
GND
GND
GND
V
CC
TO_NODE[4]+
Agilent
HDMP-0450
G
G
G
G
V
CC
HS[4]
FM_NODE[4]+
V
CC
HS[0]
TO_NODE[0]–
TO_NODE[4]–
FM_NODE[4]–
TO_NODE[0]+
FM_NODE [1]–
FM_NODE [1]+
V
CC
HS[1]
TO_NODE [1]–
TO_NODE [1]+
FM_NODE [0]–
FM_NODE [0]+
G
B
B
B
B
B
S
V
C
T
T
F
F
T
T
F
F
V
C
H
V
C
H
nnnn-nnn Rz.zz
S YYWW
nnnn-nnn= WAFER LOT – BUILD NUMBER
Rz.zz= DIE REVISION
S= SUPPLIER CODE
YYWW= DATE CODE (YY= YEAR, WW= WORK WEEK)
COUNTRY= COUNTRY OF MANUFACTURE (ON BACK SIDE)
40
44 43 42 41
39 38 37 36 35 34
1
2
3
4
5
6
7
8
9
10
33
32
31
30
29
28
27
26
25
24
11
GND
GND
GND
GND
GND
V
CC
G
V
C
G
V
CC
V
CC
V
CC
V
CC
V
C
V
C
CAPACITORS = 0.1 μF (EXCEPT WHERE NOTED).
23
12 13 14 15 16 17 18 19 20 21 22
HDMP-0450
40
44 43 42 41
39 38 37 36 35 34
1
2
3
4
5
6
7
8
9
10
33
32
31
30
29
28
27
26
25
24
11
G
G
G
10 μF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-0452 | Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops |
| HDMP-0552 | AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA VALID DETECTION |
| HDMP-1637A | Gigabit Ethernet Serialize/Deserialize (SerDes) with Differential PECL Clock Inputs(帶差分PECL時(shí)鐘輸入的千兆位以太網(wǎng)串行器/解串行器) |
| HDMP-1638 | Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs(帶雙路串行I/O和差分PECL時(shí)鐘輸入的千兆位以太網(wǎng)收發(fā)器) |
| HDMP-2689 | Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-0451 | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0451G | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0452 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops |
| HDMP-0480 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Octal Cell Port Bypass Circuit without Clock and Data Recovery |
| HDMP-0482 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Octal Cell Port Bypass Circuit with CDR and Data Valid Detection |
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