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參數資料
| 型號： | HDMP-0450 |
| 英文描述： | Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops |
| 中文描述： | 四端口旁路電路的光纖通道仲裁環(huán)路 |
| 文件頁數： | 7/10頁 |
| 文件大小： | 269K |
| 代理商： | HDMP-0450 |
7
Simplified I/O Cells
Figure 5. O-LVTTL and I-LVTTL simplified circuit schematic.
Figure 6. HS_OUT and HS_IN simplified circuit schematic.
V
BB
1.4 V
GND
V
CC
ESD
PROTECTION
GND
V
CC
O_LVTTL
I_LVTTL
GND
ESD
PROTECTION
V
CC
V
CC
HS_OUT
0.01 μF
0.01 μF
V
CC
HS
GND
ESD
PROTECTION
TO_NODE[n]–
TO_NODE[n]+
GND
FM_NODE[n]+
FM_NODE[n]–
ESD
PROTECTION
+
–
+
–
HS_IN
2*Z0 = 150
V
CC
GND
GND
V
CC
NOTE:
FM_NODE[n] INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT.
Z0 = 75
Z0 = 75
75
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相關代理商/技術參數 |
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|---|---|
| HDMP-0451 | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0451G | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0452 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops |
| HDMP-0480 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Octal Cell Port Bypass Circuit without Clock and Data Recovery |
| HDMP-0482 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Octal Cell Port Bypass Circuit with CDR and Data Valid Detection |
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