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參數(shù)資料
| 型號(hào)： | HDMP-0450 |
| 英文描述： | Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops |
| 中文描述： | 四端口旁路電路的光纖通道仲裁環(huán)路 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 269K |
| 代理商： | HDMP-0450 |
6
AC Electrical Specifications
V
CC
= 3.15 V to 3.45 V
Symbol
T
LOOP_LAT
T
CELL_LAT
t
r,LVTTLin
t
f,LVTTLin
t
r,LVTTout
t
f,LVTTout
t
rs,HS_OUT
t
fs,HS_OUT
t
rd,HS_OUT
t
fd,HS_OUT
V
IP,HS_IN
V
OP,HS_OUT
Parameter
Total Loop Latency from FM_NODE[0] to TO_NODE[0]
Per Cell Latency from FM_NODE[4] to TO_NODE[0]
Input LVTTL Rise Time Requirement, 0.8 V to 2.0 V
Input LVTTL Fall Time Requirement, 2.0 V to 0.8 V
Output TTL Rise Time, 0.8 V to 2.0 V, 10 pF Load
Output TTL Fall Time, 2.0 V to 0.8 V, 10 pF Load
HS_OUT Single-Ended Rise Time, 20%-80%
HS_OUT Single-Ended Fall Time, 20%-80%
HS_OUT Differential Rise Time, 20%-80%
HS_OUT Differential Fall Time, 20%-80%
HS_IN Required Peak-to-Peak Differential Input Voltage
HS_OUT Peak-to-Peak Differential Output Voltage
(Z0 = 75
, Figure 6)
Units
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
mV
mV
Min.
Typ.
2.0
0.8
2.0
2.0
1.7
1.7
200
200
200
200
1200
1400
Max.
3.3
2.4
300
300
300
300
2000
2000
200
1100
Guaranteed Operating Rates
V
CC
= 3.15 V to 3.45 V
FC Serial Clock Rate (MBd)
Min.
1,040
GE Serial Clock Rate (MBd)
Min.
1,240
Max.
1,080
Max.
1,260
Figure 4. Eye diagram of TO_NODE[1]
±
high speed differential output (50
termination).
Note:
Measurement taken with a 2^7-1 PRBS input to FM_NODE[1]
±
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-0451 | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0451G | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0452 | 制造商:AGILENT 制造商全稱(chēng):AGILENT 功能描述:Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops |
| HDMP-0480 | 制造商:AGILENT 制造商全稱(chēng):AGILENT 功能描述:Octal Cell Port Bypass Circuit without Clock and Data Recovery |
| HDMP-0482 | 制造商:AGILENT 制造商全稱(chēng):AGILENT 功能描述:Octal Cell Port Bypass Circuit with CDR and Data Valid Detection |
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