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參數(shù)資料
| 型號(hào)： | HDMP-0450 |
| 英文描述： | Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops |
| 中文描述： | 四端口旁路電路的光纖通道仲裁環(huán)路 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 269K |
| 代理商： | HDMP-0450 |
3
Figure 2. Connection diagram for Disk Array applications.
Figure 3. Connection diagram for multiple HDMP-0450s.
T
F
B
1
0
1
0
SERDES
HARD DISK A
T
F
B
1
0
T
F
B
1
0
2
T
F
B
1
0
3
T
F
B
1
0
4
HARD DISK B
HARD DISK C
HARD DISK D
SERDES
SERDES
SERDES
BLL
EQU
TTL
BLL
EQU
TTL
BLL
EQU
TTL
BLL
EQU
TTL
BLL
EQU
TTL
T
F
B
1
0
1
0
SERDES
HARD DISK A
T
F
B
1
0
T
F
B
1
0
2
T
F
B
1
0
3
T
F
B
1
0
4
HARD DISK B
HARD DISK C
HARD DISK D
SERDES
SERDES
SERDES
BLL
EQU
TTL
BLL
EQU
TTL
BLL
EQU
TTL
BLL
EQU
TTL
BLL
EQU
TTL
T
F
B
1
0
1
0
T
F
B
1
0
T
F
B
1
0
2
T
F
B
1
0
3
T
F
B
1
0
4
HARD DISK E
HARD DISK F
HARD DISK G
SERDES
SERDES
SERDES
BLL
EQU
TTL
BLL
EQU
TTL
BLL
EQU
TTL
BLL
EQU
TTL
BLL
EQU
TTL
HARD DISK H
SERDES
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-0452 | Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops |
| HDMP-0552 | AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA VALID DETECTION |
| HDMP-1637A | Gigabit Ethernet Serialize/Deserialize (SerDes) with Differential PECL Clock Inputs(帶差分PECL時(shí)鐘輸入的千兆位以太網(wǎng)串行器/解串行器) |
| HDMP-1638 | Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs(帶雙路串行I/O和差分PECL時(shí)鐘輸入的千兆位以太網(wǎng)收發(fā)器) |
| HDMP-2689 | Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-0451 | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0451G | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0452 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops |
| HDMP-0480 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Octal Cell Port Bypass Circuit without Clock and Data Recovery |
| HDMP-0482 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Octal Cell Port Bypass Circuit with CDR and Data Valid Detection |
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