
PMU & PLL
7-5
GMS30C7201 Data Sheet
7.3
Power management states
Run
The system is running normally. All Clocks running (except where gated locally). The
SDRAM controller is performing normal refresh.
SLOW
The CPU is switched into FastBus mode, and hence runs at the BCLK rate (half the
FCLK rate). This is the default mode after exiting SLEEP Mode.
IDLE
In this mode, the PMU becomes the bus master until there is either a fast or normal
interrupt for the CPU, or the peripheral DMA controller requests master-ship of the bus.
This will cause the clocks in the CPU to stop when it attempts an ASB access. Entry
to this mode can be caused by the CPU writing the PMU_IDLE value to the PMU Mode
Register when in RUN or SLOW modes, or a WakeUp signal becoming active when the
PMU is SLEEP or DEEP SLEEP modes
SLEEP
In this mode, the SDRAM is put into self-refresh mode, and internal clocks are gated
off. This mode can only be entered from IDLE mode (the PMU bus master must have
mastership of the ASB before this mode can be entered). The PMU must be bus master
to ensure that the system is stopped in a safe state, and is not half way through an
SDRAM write (for example). Both the Video and Communication clocks should be
disabled before entering this state.
Usually this state would only be entered briefly, on the way to entering DEEP SLEEP
mode.
DEEP SLEEP
In DEEP SLEEP mode, the 3.6864MHz oscillator and the PLL are disabled. This is the
lowest power state available. Only the 32KHz oscillator runs. The real time clock and
the PMU are clocked from this clock. Clocked circuitry in the PMU runs from 4kHz (ie
the RTC clock divided by 8). Everything else is powered down, and SDRAM is in self-
refresh mode. This is the normal system
“
off
”
mode.
SLEEP and DEEP SLEEP modes are exited either by a user wake-up event (generally
pressing the
“
On
”
key), or by an RTC wake-up alarm, or by a modem ring indicate
event. These interrupt sources go directly to the PMU.