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參數(shù)資料
| 型號： | GMS30C7201 |
| 英文描述： | 32-Bit RISC Microprocessor(32位 RISC 微處理器) |
| 中文描述： | 32位RISC微處理器（32位的RISC微處理器） |
| 文件頁數(shù)： | 201/354頁 |
| 文件大小： | 1639K |
| 代理商： | GMS30C7201 |
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Fast AMBA Peripherals
12-45
GMS30C7201 Data Sheet
After the FIr is enabled for 4.0Mbps transmission, the receiver logic begins by selecting
an arbitrary symbol boundary, receives four incoming 4PPM symbols from the input
pin
using a serial shifter, and latches and decodes the symbols one at a time. If the symbols
do not decode to the correct preamble, the chip counter
’
s clock is forced to skip one
8MHz period, effectively delaying the chip count by one. This process is repeated until
the preamble is recognized, signifying that the chip counter is synchronized. The
preamble may be repeated as few as sixteen times, or may be continuously repeated
to indicate an idle receive line.
At any time after the transmission of sixteen preambles, the start flag may be received.
The start flag is eight symbols long. If any portion of the start flag does not match the
standard encoding, the receive logic signals a framing error and the receive logic once
again begins to look for the frame preamble.
Once the correct start flag is recognized, each subsequent grouping of four DDs is
decoded into a data byte, placed within a five byte temporary buffer which is used to
prevent the CRC from being placed within the receive buffer. When the temporary buffer
is filled, data values are pushed out one by one to the receive buffer. The first data byte
of a frame is the address. If receiver address matching is enabled, the received address
is compared to the address programmed in the address match value field in one of the
control registers. If the two values are equal or if the incoming address contains all
ones, all subsequent data bytes including the address byte are stored in the receive
buffer. If the values do not match, the receiver logic does not store any data in the
receive buffer, ignores the remainder of the frame, and begins to search for the next
preamble. The second data byte of the frame can contain an optional control field as
defined by the user and must be decoded in software (There is no hardware support
within the FIr).
Frames can contain any amount of data in multiples of 8-bits up to a maximum of 2047
bytes (including the address and control byte). The FIr does not limit frame size, thus it
is the responsibility of the user to check that the size of each incoming frame does not
exceed the IrDA protocol
’
s maximum allowed frame size.
When the receive buffer is filled, an interrupt or DMA transfer is signalled. If the data is
not removed quickly enough, an overrun error is signalled when the receive logic
attempts to place additional data into the full buffer. Once the buffer is full, all
subsequent data bytes received are lost while all buffer contents remain intact.
If any two sequential symbols within the data field do not contain pulses (are 0000), the
frame is aborted, the least recent or oldest byte within the temporary buffer is moved to
the receive buffer (the remaining four buffer entries are discarded), the end of frame
(EOF) tag is set within the same buffer entry where the last
“
good
”
byte of data resides,
and the receiver logic begins to search for the preamble. An abort also occurs if any
data symbol containing 0011, 1010, 0101, or 1001 occurs (invalid symbols which do
not occur in the stop flag).
The receive logic continuously searches for the 8-symbol stop flag. Once it is
recognized, the last byte which was placed within the receive buffer is flagged as the
last byte of the frame and the data in the temporary buffer is removed and used as the
32-bit CRC value for the frame. Instead of placing this in the receive buffer, the receive
logic compares it to the CRC-32 value which is continuously calculated using the
incoming data stream. If they do not match, the last byte which was placed within the
receive buffer is also tagged with a CRC error. The CRC value is not placed in the
receive buffer.
If the user disables the FIr
’
s receiver during operation, reception of the current data byte
is stopped immediately, the serial shifter and receive buffer are cleared, and all clocks
used by the receive logic are automatically shut off to conserve power.
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|---|---|
| GMS-32H | 制造商:Carlo Gavazzi 功能描述:Manual Motor Starter |
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| GMS-32H 0.16A | 制造商:Carlo Gavazzi 功能描述:MMS UP TO 32A HIGH BREAK 0.1-0.16A |
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| GMS-32H 0.4A | 制造商:Carlo Gavazzi 功能描述:MMS UP TO 32A HIGH BREAK 0.25-0.4A |
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