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參數(shù)資料
| 型號： | EP20K60ETI144-3ES |
| 元件分類： | 電源監(jiān)測 |
| 英文描述： | Dual Voltage Monitor with Intergrated CPU Supervisor |
| 中文描述： | 雙電壓監(jiān)視器集成CPU監(jiān)控 |
| 文件頁數(shù)： | 58/114頁 |
| 文件大小： | 1623K |
| 代理商： | EP20K60ETI144-3ES |
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48
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to CLK2p. Table 14 shows the
combinations supported by the ClockLock and ClockBoost circuitry. The
CLK2p
pin can feed both the ClockLock and ClockBoost circuitry in the
APEX 20K device. However, when both circuits are used, the other clock
pin (CLK1p) cannot be used.
APEX 20KE ClockLock Feature
APEX 20KE devices include an enhanced ClockLock feature set. These
devices include up to four PLLs, which can be used independently. Two
PLLs are designed for either general-purpose use or LVDS use (on devices
that support LVDS I/O pins). The remaining two PLLs are designed for
general-purpose use. The EP20K200E and smaller devices have two PLLs;
the EP20K300E and larger devices have four PLLs.
The following sections describe some of the features offered by the
APEX 20KE PLLs.
External PLL Feedback
The ClockLock circuit’s output can be driven off-chip to clock other
devices in the system; further, the feedback loop of the PLL can be routed
off-chip. This feature allows the designer to exercise fine control over the
I/O interface between the APEX 20KE device and another high-speed
device, such as SDRAM.
Clock Multiplication
The APEX 20KE ClockBoost circuit can multiply or divide clocks by a
programmable number. The clock can be multiplied by m/(n
× k) or
m/(n
× v), where m and k range from 2 to 160, and n and vrange from 1 to
16. Clock multiplication and division can be used for time-domain
multiplexing and other functions, which can reduce design LE
requirements.
Table 14. Multiplication Factor Combinations
Clock 1
Clock 2
×1
×1, ×2
×2
×1, ×2, ×4
×4
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