參數(shù)資料
型號(hào): EP20K60ETI144-3ES
元件分類: 電源監(jiān)測(cè)
英文描述: Dual Voltage Monitor with Intergrated CPU Supervisor
中文描述: 雙電壓監(jiān)視器集成CPU監(jiān)控
文件頁數(shù): 45/114頁
文件大?。?/td> 1623K
代理商: EP20K60ETI144-3ES
36
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
f For more information on APEX 20KE devices and CAM, see Application
Driving Signals to the ESB
ESBs provide flexible options for driving control signals. Different clocks
can be used for the ESB inputs and outputs. Registers can be inserted
independently on the data input, data output, read address, write
address, WE, and RE signals. The global signals and the local interconnect
can drive the WE and RE signals. The global signals, dedicated clock pins,
and local interconnect can drive the ESB clock signals. Because the LEs
drive the local interconnect, the LEs can control the WE and RE signals and
the ESB clock, clock enable, and asynchronous clear signals. Figure 24
shows the ESB control signal generation logic.
Figure 24. ESB Control Signal Generation
Note:
(1)
APEX 20KE devices have four dedicated clocks.
An ESB is fed by the local interconnect, which is driven by adjacent LEs
(for high-speed connection to the ESB) or the MegaLAB interconnect. The
ESB can drive the local, MegaLAB, or FastTrack Interconnect routing
structure to drive LEs and IOEs in the same MegaLAB structure or
anywhere in the device.
RDEN
WREN
INCLOCK
INCLKENA
OUTCLOCK
OUTCLKENA
Dedicated
Clocks
Global
Signals
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
2 or 4
4
Local
Interconnect
Local
Interconnect
INCLR OUTCLR
(1)
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