參數(shù)資料
型號: EP20K60ETI144-3ES
元件分類: 電源監(jiān)測
英文描述: Dual Voltage Monitor with Intergrated CPU Supervisor
中文描述: 雙電壓監(jiān)視器集成CPU監(jiān)控
文件頁數(shù): 49/114頁
文件大?。?/td> 1623K
代理商: EP20K60ETI144-3ES
4
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
Altera MegaCore functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
NativeLinkTM integration with popular synthesis, simulation,
and timing analysis tools
Quartus II SignalTapTM embedded logic analyzer simplifies
in-system design evaluation by giving access to internal nodes
during device operation
Supports popular revision-control software packages including
PVCS, Revision Control System (RCS), and Source Code Control
System (SCCS )
Table 4. APEX 20K QFP, BGA & PGA Package Options & I/O Count
Device
144-Pin
TQFP
208-Pin
PQFP
RQFP
240-Pin
PQFP
RQFP
356-Pin BGA 652-Pin BGA 655-Pin PGA
EP20K30E
92
125
EP20K60E
92
148
151
196
EP20K100
101
159
189
252
EP20K100E
92
151
183
246
EP20K160E
88
143
175
271
EP20K200
144
174
277
EP20K200E
136
168
271
376
EP20K300E
152
408
EP20K400
502
EP20K400E
488
EP20K600E
488
EP20K1000E
488
EP20K1500E
488
相關PDF資料
PDF描述
EP20K100ERI208-1ES Single Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 8-MSOP
EP20K100ERI208-2ES Single Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 8-MSOP
EP20K100ERI208-3ES FPGA
EP20K100ERI240-1ES FPGA
EP20K100ERI240-2ES FPGA
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