參數(shù)資料
型號： EP20K60ERC208
廠商： ALTERA CORP
元件分類： PLD
英文描述： LOADABLE PLD, PQFP208
封裝： 30.40 X 30.40 MM, 0.50 MM PITCH, RQFP-208
文件頁數(shù)： 87/114頁
文件大?。?/td> 4116K
代理商： EP20K60ERC208
IGLOO nano DC and Switching Characteristics
2- 60
Advance v0.2
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be
driven and conditioned internally by the CCC module. For more details on clock conditioning
Table 2-88 on page 2-64 present minimum and maximum global clock delays within each device.
Minimum and maximum delays are measured with minimum and maximum loading.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-80 AGLN010 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input LOW Delay for Global Clock
1.08
1.36
ns
tRCKH
Input HIGH Delay for Global Clock
1.09
1.44
ns
tRCKMPWH
Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL
Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.35
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-81 AGLN015 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input LOW Delay for Global Clock
1.15
1.49
ns
tRCKH
Input HIGH Delay for Global Clock
1.16
1.59
ns
tRCKMPWH
Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL
Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.42
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K60ERC208-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERC208-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERC208-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERC240-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERC240-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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