參數(shù)資料
型號(hào)： EP20K60ERC208
廠商： ALTERA CORP
元件分類： PLD
英文描述： LOADABLE PLD, PQFP208
封裝： 30.40 X 30.40 MM, 0.50 MM PITCH, RQFP-208
文件頁數(shù)： 61/114頁
文件大小： 4116K
代理商： EP20K60ERC208
IGLOO nano DC and Switching Characteristics
2- 36
Advance v0.2
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose
1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer.
Timing Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-58 Minimum and Maximum DC Input and Output Levels
1.2 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL
1 I
IH
2
Drive
Strength
Min.,
V
Max.,
V
Min., V
Max., V
Min., V
mA mA Max., mA3 Max., mA3 A4 A4
1 mA
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI 1
1
TBD
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI.
Input current is larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-11 AC Loading
Table 2-59 1.2 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
CLOAD (pF)
01.2
0.6
5
* Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.
Test Point
Enable Path
Datapath
5 pF
R = 1 k
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Table 2-60 1.2 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
1 mA
STD
1.55
10.33 0.26
1.56
1.66
1.10
8.52
7.30
3.00
3.12
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-61 1.2 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
1 mA
STD
1.55
4.47
0.26
1.56
1.66
1.10
3.56
3.18
3.00
3.25
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
相關(guān)PDF資料
PDF描述
EP20K60ERC240 LOADABLE PLD, PQFP240
EP20K60ETC144 LOADABLE PLD, PQFP144
EP2645ETTS-33.178MTR CRYSTAL OSCILLATOR, CLOCK, 33.178 MHz, HCMOS OUTPUT
EP2600ETPD-FREQ1TR CRYSTAL OSCILLATOR, CLOCK, 1 MHz - 50 MHz, HCMOS OUTPUT
EP2600ETPD-FREQ1 CRYSTAL OSCILLATOR, CLOCK, 1 MHz - 50 MHz, HCMOS OUTPUT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K60ERC208-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERC208-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERC208-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERC240-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERC240-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*