參數資料
型號: EP20K60ERC208
廠商: ALTERA CORP
元件分類: PLD
英文描述: LOADABLE PLD, PQFP208
封裝: 30.40 X 30.40 MM, 0.50 MM PITCH, RQFP-208
文件頁數: 113/114頁
文件大?。?/td> 4116K
代理商: EP20K60ERC208
IGLOO nano DC and Switching Characteristics
2- 84
Advance v0.2
Part Number and Revision Date
Part Number 51700110-002-1
Revised November 2008
List of Changes
The following table lists critical changes that were made in the current version of the chapter.
Actel Safety Critical, Life Support, and High-Reliability
Applications Policy
The Actel products described in this advance status datasheet may not have completed Actel’s
qualification process. Actel may amend or enhance products during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the
responsibility of each customer to ensure the fitness of any Actel product (but especially a new
product) for a particular purpose, including appropriateness for safety-critical, life-support, and
other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability
exclusions relating to life-support applications. A reliability report covering all of Actel’s products is
available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also
offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your
local Actel sales office for additional reliability information.
Previous Version
Changes in Current Version (Advance v0.2)
Page
Advance v0.1
(October 2008)
The table notes and references were revised in Table 2-2 Recommended
Operating Conditions 1. VMV was included with VCCI and a table note was added
stating, "VMV pins must be connected to the corresponding VCCI pins. See Pin
Descriptions for further information." Please review carefully.
VJTAG was added to the list in the table note for Table 2-8 Quiescent Supply
added for AGLN010, AGLN015, and AGLN030 for 1.5 V.
VCCI was removed from the list in the table note for Table 2-9 Quiescent Supply
Values for ICCA current were updated for AGLN010, AGLN015, and AGLN030 in
Values for PAC1 and PAC2 were added to Table 2-14 Different Components
Table notes regarding wide range support were added to Table2-20Summary
1.2 V LVCMOS wide range values were added to Table 2-21 Summary of
The following table note was added to Table 2-24 Summary of I/O Timing
macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B
specification."
3.3 V LVCMOS Wide Range and 1.2 V Wide Range were added to Table 2-27 I/O
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相關代理商/技術參數
參數描述
EP20K60ERC208-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERC208-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERC208-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERC240-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERC240-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA