參數(shù)資料
型號: EP20K60ERC208
廠商: ALTERA CORP
元件分類: PLD
英文描述: LOADABLE PLD, PQFP208
封裝: 30.40 X 30.40 MM, 0.50 MM PITCH, RQFP-208
文件頁數(shù): 103/114頁
文件大小: 4116K
代理商: EP20K60ERC208
IGLOO nano DC and Switching Characteristics
Ad vance v0.2
2-75
1.2 V DC Core Voltage
Table 2-96 RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
Description
Std.
Units
tAS
Address setup time
1.53
ns
tAH
Address hold time
0.29
ns
tENS
REN_B, WEN_B setup time
1.50
ns
tENH
REN_B, WEN_B hold time
0.29
ns
tBKS
BLK_B setup time
3.05
ns
tBKH
BLK_B hold time
0.29
ns
tDS
Input data (DI) setup time
1.33
ns
tDH
Input data (DI) hold time
0.66
ns
tCKQ1
Clock HIGH to new data valid on DO (output retained, WMODE = 0)
6.61
ns
Clock HIGH to new data valid on DO (flow-through, WMODE = 1)
5.72
ns
tCKQ2
Clock HIGH to new data valid on DO (pipelined)
3.38
ns
tC2CWWL
Address collision clk-to-clk delay for reliable write after write on same address;
applicable to closing edge
0.30
ns
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same
address; applicable to opening edge
0.89
ns
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same
address; applicable to opening edge
1.01
ns
tRSTBQ
RESET_B LOW to data out LOW on DO (flow-through)
3.86
ns
RESET_B LOW to data out LOW on DO (pipelined)
3.86
ns
tREMRSTB
RESET_B removal
1.12
ns
tRECRSTB
RESET_B recovery
5.93
ns
tMPWRSTB
RESET_B minimum pulse width
1.18
ns
tCYC
Clock cycle time
10.90
ns
FMAX
Maximum frequency
92
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
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