參數(shù)資料
型號(hào)： EP1K50FI256-2N
廠商： Altera
文件頁(yè)數(shù)： 8/86頁(yè)
文件大?。?/td> 0K
描述： IC ACEX 1K FPGA 50K 256-FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 90
系列： ACEX-1K®
LAB/CLB數(shù)： 360
邏輯元件/單元數(shù)： 2880
RAM 位總計(jì)： 40960
輸入/輸出數(shù)： 186
門數(shù)： 199000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FBGA（17x17）
16
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 8. ACEX 1K Logic Element
The programmable flipflop in the LE can be configured for D, T, JK, or SR
operation. The clock, clear, and preset control signals on the flipflop can
be driven by global signals, general-purpose I/O pins, or any internal
logic. For combinatorial functions, the flipflop is bypassed and the LUT’s
output drives the LE’s output.
The LE has two outputs that drive the interconnect: one drives the local
interconnect, and the other drives either the row or column FastTrack
Interconnect routing structure. The two outputs can be controlled
independently. For example, the LUT can drive one output while the
register drives the other output. This feature, called register packing, can
improve LE utilization because the register and the LUT can be used for
unrelated functions.
The ACEX 1K architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. The carry chain supports high-
speed counters and adders, and the cascade chain implements wide-input
functions with minimum delay. Carry and cascade chains connect all LEs
in a LAB and all LABs in the same row. Intensive use of carry and cascade
chains can reduce routing flexibility. Therefore, the use of these chains
should be limited to speed-critical portions of a design.
To LAB Local
Interconnect
Carry-In
Clock
Select
Carry-Out
Look-Up
Table
(LUT)
Clear/
Preset
Logic
Carry
Chain
Cascade
Chain
Cascade-In
Cascade-Out
To FastTrack
Interconnect
Programmable
Register
PRN
CLRN
DQ
ENA
Register Bypass
data1
data2
data3
data4
labctrl1
labctrl2
labctrl4
labctrl3
Chip-Wide
Reset
相關(guān)PDF資料
PDF描述
EP1K50FI256-2 IC ACEX 1K FPGA 50K 256-FBGA
EP1K50FC256-1N IC ACEX 1K FPGA 50K 256-FBGA
A54SX32A-FFGG144 IC FPGA SX 48K GATES 144-FBGA
A54SX32A-FFG144 IC FPGA SX 48K GATES 144-FBGA
ABC50DREN-S13 CONN EDGECARD 100PS .100 EYELET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K50FI256-2P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI256-2X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI256-3F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-1DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-1F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*