參數(shù)資料
型號: EP1K50FI256-2N
廠商: Altera
文件頁數(shù): 28/86頁
文件大?。?/td> 0K
描述: IC ACEX 1K FPGA 50K 256-FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 90
系列: ACEX-1K®
LAB/CLB數(shù): 360
邏輯元件/單元數(shù): 2880
RAM 位總計: 40960
輸入/輸出數(shù): 186
門數(shù): 199000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FBGA(17x17)
34
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Column-to-IOE Connections
When an IOE is used as an input, it can drive up to two separate column
channels. When an IOE is used as an output, the signal is driven by a
multiplexer that selects a signal from the column channels. Two IOEs
connect to each side of the column channels. Each IOE can be driven by
column channels via a multiplexer. The set of column channels is different
for each IOE (see Figure 17).
Figure 17. ACEX 1K Column-to-IOE Connections
Note:
(1)
The values for m and n are shown in Table 9.
Table 9 lists the ACEX 1K column-to-IOE interconnect resources.
Table 9. ACEX 1K Column-to-IOE Interconnect Resources
Device
Channels per Column (n)
Column Channels per Pin (m)
EP1K10
24
16
EP1K30
24
16
EP1K50
24
16
EP1K100
24
16
Each IOE is driven by
a m-to-1 multiplexer
Each IOE can drive two
column channels.
Column
Interconnect
n
m
n
IOE1
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