參數(shù)資料
型號： ELANSC410
英文描述： Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; Temperature Range: 0&degC to 70°C; Package: 16-QFN
中文描述： ElanSC410 - ElanSC410框圖
文件頁數(shù)： 68/119頁
文件大?。?/td> 1167K
代理商： ELANSC410
52
lanSC310 Microcontroller Data Sheet
PREL IMINARY
data onto the parallel port data bus, as shown in
When the lanSC310 microcontroller parallel port is
configured for Bidirectional mode operation, the
PPDWE pin is reconfigured via firmware to function as
the Parallel Port Data Register address decode
(PPDCS). The PPOEN output from the lanSC310 mi-
crocontroller is controlled via the Parallel Port Control
Register Bit 5. This signal is then used to control the
output enable of the external parallel port data latch. By
setting this bit, the parallel port data latch is disabled,
and then data can be transferred from an external par-
allel port device into the lanSC310 microcontroller
through an external 244 type buffer. A typical bidirec-
tional Parallel Port Data Bus implementation is shown
If the VCC5 supply pins are connected to a 5-V power
supply, then the Parallel Port control signals will be
driven by 5-V outputs and can be connected directly to
the parallel port connector. If VCC5 is connected to
3.3 V, the parallel port control signals should be trans-
lated to 5 V.
The lanSC310 CPU also supports Enhanced Parallel
Port (EPP) mode. The EPP mode pins are defined in
In Normal mode, the outputs shown in Table 24 func-
tion as open-collector or open-drain outputs. In EPP
mode, these outputs must function as standard CMOS
outputs that are driven High and Low. Figure 6 shows
the design that should be used to support EPP mode.
Figure 5.
lanSC310 Microcontroller
Unidirectional Parallel Port Data Bus
Implementation
374 Octal D Flip Flop
SD7–SD0
PPDWE
Parallel Port
Data Bus
CLK
OE
DQ
Table 24.
Parallel Port EPP Mode Pin Definition
Normal
Mode
EPP
Mode
Description
STRB
WRITE
EPP write signal. This signal is
driven active during writes to
the EPP data or address regis-
ter.
AFDT
DSTRB
EPP data strobe. This signal is
driven active during reads or
writes to the EPP data register.
SLCTIN
ASTRB
EPP address strobe. This sig-
nal is driven active during
reads or writes to the EPP ad-
dress register.
ACK
INTR
EPP interrupt. This signal is an
input used by the EPP device
to request service.
BUSY
WAIT
EPP wait. This signal is used to
add wait states to the current
cycle. It is similar to the ISA IO-
CHRDY signal.
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參數(shù)描述
ELANSC410-100AC 制造商:Advanced Micro Devices 功能描述:MCU 16-Bit/32-Bit Elan CISC ROMLess 3.3V 292-Pin BGA
ELANSC410-100ACAD 制造商:Advanced Micro Devices 功能描述:
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