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參數(shù)資料
| 型號(hào)： | ELANSC410 |
| 英文描述： | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; Temperature Range: 0°C to 70°C; Package: 16-QFN |
| 中文描述： | ElanSC410 - ElanSC410框圖 |
| 文件頁(yè)數(shù)： | 52/119頁(yè) |
| 文件大?。?/td> | 1167K |
| 代理商： | ELANSC410 |
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38
lanSC310 Microcontroller Data Sheet
PREL IMINARY
VCC
3.3 V DC Supply Pins
These supply pins provide power to the lanSC310 mi-
crocontroller core. Refer to AC Characteristics for VCC
power up timing restrictions.
The VCC pins are required for battery backup. For
more information about battery backup, see the
lanTMSC300 and lanTMSC310 Microcontrollers Solu-
tion For Systems Using a Back-Up Battery Application
Note, order #20746.
VCC1
3.3 V or 5 V Supply Pin
This supply pin provides power to a subset of the local
bus, power management, and ISA interface pins.
VCC5
5 V DC Supply Pins
These supply pins provide power to the 5 V only inter-
face pins. These pins could be 3.3 V in a pure 3.3-V
system.
VMEM
3.3 V or 5 V Supply Pins
These supply pins provide power to the Memory Inter-
face and Data Bus pins (D15–D0). These pins must be
connected to the same DC supply as the system
DRAMs.
VSYS
3.3 V or 5 V Supply Pins
These supply pins provide power to a subset of the ISA
address and command signal pins, in addition to exter-
nal memory chip selects, buffer direction controls, and
other miscellaneous functions.
VSYS2
3.3-V or 5-V Supply Pins
These supply pins provide power to some of the
lanSC310 microcontroller alternate system interface
pins.
FUNCTIONAL DESCRIPTION
The lanSC310 microcontroller architecture consists
of several components, as shown in the device block
diagram. These components can be grouped into
seven main functional modules:
1. The Am386SXLV microprocessor core itself, includ-
ing System Management Mode (SMM) power man-
agement hardware
2. A memory controller and associated mapping hard-
ware
3. An additional power management controller that in-
terfaces to the CPU’s SMM and is integrated tightly
with internal clock generator hardware
4. Core peripheral controllers (DMA, interrupt control-
ler, and timer)
5. Additional peripheral controllers (UART, parallel
port, and real-time clock)
6. PC/AT support features
7. Optional local bus controller or optional maximum
ISA bus
The remainder of this section describes these mod-
ules.
Am386SXLV CPU Core
The CPU core component is a full implementation of
the AMD Am386SXLV 32-bit, low-voltage microproces-
sor (with I/O pads removed). For more information
about the A m386 mic r opr oc esso r s , s ee the
Am386SX/SXL/SXLV Data Sheet, order #21020 and
the
AM386DX/DXL Data Sheet, order #21017.
Along with standard 386 architectural features, the
CPU core includes SMM. SMM and the other features
of the CPU are described in the
Am386DXLV and
Am386SXLV Microprocessors Technical Reference
Manual, order #16944.
Memory Controller
The lanSC310 microcontroller memory controller is a
unified control unit that supports a high-performance,
16-bit data path to DRAM or SRAM. No external mem-
ory bus buffers are required and up to 16 Mbyte in two
16-bit banks can be supported. System memory must
always be configured as 16-bits wide. For more infor-
mation about the memory controller, refer to Chapter 2
of the
lanTMSC310 Microcontroller Programmer’s
Reference Manual, order #20665. Figure 7 on page 55
shows a typical embedded PC memory configuration.
The lanSC310 microcontroller’s memory controller
supports an EMS-compatible Memory Mapping Sys-
tem (MMS) with 12 page registers. This facility can be
used to provide access to ROM-based software.
Shadow RAM is also supported.
The Memory Controller supports one of three different
memory operating modes: SRAM, Page mode DRAM
or Enhanced Page mode DRAM. Enhanced Page
mode increases DRAM access performance by effec-
tively doubling the DRAM page size in a two-bank
DRAM system by arranging the address lines such that
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