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參數(shù)資料
| 型號(hào)： | ELANSC310 |
| 英文描述： | Elan SC310 - Elan SC310 Single-Chip. 32-Bit. PC/AT Microcontroller |
| 中文描述： | 義隆SC310 -伊蘭SC310單芯片。 32位。的PC / AT單片機(jī) |
| 文件頁(yè)數(shù)： | 70/119頁(yè) |
| 文件大?。?/td> | 1167K |
| 代理商： | ELANSC310 |
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54
lanSC310 Microcontroller Data Sheet
PREL IMINARY
ister at I/O address 070h. The default value for the NMI
enable bit is 1, which inhibits NMI generation. The NMI
enable bit (7) is a write-only bit, and is active Low. The
remaining bits of the register located at 070h (6–0) con-
trol the RTC function. Because the RTC portion of this
register is only 7 bits wide and is also write only, there
is no conflict between the two functions. This register is
discussed in more detail in the RTC section of Chapter
3 in the
lanSC310 Microcontroller Programmer’s Ref-
erence Manual, order #20665.
Speaker Interface
The PC/AT standard tone generation interface for the
system speaker is implemented in the lanSC310 mi-
crocontroller. There are two data paths to the
SPEAKER pin of the device. The first path is driven by
the output Channel 2 of the internal 82C54 counter/
timer. The counter/timer can be programmed in various
ways to generate a waveform at the output, OUT2.
Also, the gate input of timer Channel 2 is controlled by
the T2G bit in Port B. The timer gate can be used to in-
hibit tone generation by the timer channel. The second
path is driven directly by the SPK bit in port B. This bit
can be manipulated by the CPU to generate almost any
digital waveform at the SPEAKER pin.
Fast A20 Address Control
With the lanSC310 microcontroller, full Real mode ad-
dress compatibility requires that address rollover at the
1-Mbyte address boundary be handled the same way
as the early 8088-based PCs were handled. This re-
quires the system address line 20 to have the capability
of being forced to 0 during Real mode execution. Con-
trol of the A20 line is supported from multiple sources.
The A20G signal in PC/AT systems is normally con-
nected to an output of the PC/AT keyboard controller. A
logic High on this input forces the pass through of the
CPU’s A20 onto the internal system address bus. A
logic Low on this input forces the system address bus
A20 line Low, as long as the internal A20 gate control
is not being utilized.
The lanSC310 microcontroller provides a high-perfor-
mance method for controlling the system A20 line, in-
dependent of the relatively slow PC/AT keyboard
controller. This internal A20 gate control is generated
by the Miscellaneous 1 Register, Index 6Fh, and Port
92h.
For more information about A20 gate control, see the
lanTMSC300 and lanSC310 Microcontrollers
GATEA20 Function Clarification Application Note,
order #21811.
Reset Control
An external hardware reset is required in order to cor-
rectly initialize internal logic after system power-up.
See the required timings in Table 45 on page 88. Sys-
tem power supplies typically have a POWERGOOD
output signal that is used as an active Low asynchro-
nous reset input for the device. IORESET is intended
to be driven by a POWERGOOD-compatible signal.
When IORESET is driven Low, the lanSC310 micro-
controller resets all of its internal logic with the excep-
tion of the RTC Valid Data/Time bit (Register D, RTC
Index 0Dh, bit 7) and some internal register configura-
tion bits. The RESIN input is intended to be driven by a
signal that indicates that the battery back-up source
has been disconnected. When RESIN is driven Low,
the lanSC310 microcontroller resets all of its internal
logic. The RESIN input buffer is a Schmitt trigger for tol-
erance of slow rise and fall times on the signal. RESIN
and IORESET are internally synchronized to the CPU
clock to provide the internal hardware reset.
For more information, see Table 23 on page 50 and
Besides the device hardware reset, the internal CPU
has several other possible reset sources. These other
sources only generate CPU reset.
In a standard PC/AT-type system, an RC (CPU Reset)
pin is typically connected to an output of the 8042 key-
board controller.
Also, an internal configuration register can be used to
reset the CPU in less time than that required by the ex-
ternal keyboard controller. The internal reset is con-
trolled by the Miscellaneous 1 Register, Index 6Fh, and
Port 92h.
The lanSC310 microcontroller provides both of the
CPU reset functions described above and also triggers
a CPU reset upon processor shutdown. If the CPU
reaches a state where it cannot continue to execute be-
cause of faults and error conditions, it will issue a status
code indicating shutdown, and the CPU will halt opera-
tion with no means of continuing except for a reset. If
this shutdown status is detected, a 16 clock minimum
pulse width reset is automatically sent to the CPU.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ELANSC310-25 | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Single-Chip, 32-Bit, PC/AT Microcontroller |
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| ELANSC310-25KI | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Single-Chip, 32-Bit, PC/AT Microcontroller |
| ELANSC310-25VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: 制造商:AMD 功能描述: |
| ELANSC310-33 | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Single-Chip, 32-Bit, PC/AT Microcontroller |
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