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lanSC310 Microcontroller Data Sheet
PREL IMINARY
DTR/CFG1
Data Terminal Ready (Output; Active Low)
This signal indicates to the external serial device that
the internal serial port controller is ready to communi-
cate.
The state of this signal is used to determine the pin
configuration at power-up. For more information, see
RIN
Ring Indicate (Input; Active Low)
This signal is used as a modem control function. A
change in state on this signal by the external serial de-
vice causes a modem status interrupt. This signal can
be used to cause the lanSC310 microcontroller to re-
sume from a suspended state.
RTS
/CFG0
Request To Send (Output; Active Low)
This signal indicates to the external serial device that
the internal serial port controller is ready to send data.
The state of this signal is used to determine the pin
configuration at power-up. For more information, see
SIN
Serial Data In (Input; Active High)
This signal is used to receive the serial data from the
external serial device into the internal serial port
controller.
SOUT
Serial Data Out (Output; Active High)
This signal is used to transmit the serial data from the
internal serial port controller to the external serial
device.
POWER MANAGEMENT INTERFACE
ACIN
AC Input Status (Input; Active High)
When asserted, this signal disables all power manage-
ment functions (if so enabled). It can be used to indi-
cate when the system is being supplied power from an
AC source.
BL4–BL1
Battery Low Detects
(Inputs; Negative Edge Sensitive)
These signals are used to indicate to the lanSC310
microcontroller the current status of the battery. BL4–
BL1 can indicate various conditions of the battery as
status changes. A High indicates normal operating
conditions, while a Low indicates a low voltage warning
condition. These inputs can be used to force the sys-
tem into one of the power saving modes when acti-
vated, as follows:
n BL1 can be programmed to force the system to go
to Low Speed PLL mode or to generate an SMI.
n BL2 can be programmed to force the system to
enter Sleep mode if not already in Sleep mode, or
to generate an SMI.
n BL3 can only be programmed to generate an SMI.
n BL4 can be programmed to force the system to
enter Suspend mode.
EXTSMI
External System Management Interrupt
(Input; Edge Sensitive)
This input is provided to allow external logic to gener-
ate an SMI request to the CPU. It is edge triggered,
with the polarity programmable.
LPH
Latched Power Control (Output; Active Low)
This signal is the inverse of BL4 if ACIN is not true and
BL4 is enabled.
PGP3–PGP0
Programmable Chip Select Generation
(Input/Output)
PGP0 and PGP1 can be programmed as input or out-
put. The default is input. PGP2 and PGP3 are output
only.
These general purpose pins can be individually pro-
grammed as decoder outputs or chip selects for other
external peripheral devices.
PGP0 and PGP2 can be gated with I/O write or act as
an address decode only. PGP1 and PGP3 can be
gated with I/O Read or act as an address decode only.
PGP0 and PGP1 can be directly controlled via a single
register bit if configured to do so. PGP2 and PGP3 can
also be configured for a specific state when the PMU is
in the off state.
PGP2 and PGP3 can be programmed to be set to a
pre-defined state for Micro Power Off mode.
For more information about PGP3–PGP0, see the
lanTMSC310 Microcontroller Programmer’s Refer-
ence Manual, order #20665 and Using 10-Bit ROMCS
Designs in lanTMSC300 and lanSC310 Microcontrol-
lers Application Note, order #21825.
PMC4–PMC0
Power Management Controls
(Output; Programmable)
The Power Management Control outputs control the
power to various external devices and system compo-
nents. The PMC0, PMC1, PMC2, and PMC4 signals