參數(shù)資料
型號: EFM32G222F128
廠商: Energy Micro
文件頁數(shù): 5/136頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 128KB FLASH 48LQFP
特色產(chǎn)品: EFM32 Gecko
標(biāo)準(zhǔn)包裝: 1
系列: Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 37
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 914-1027-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
102
www.energymicro.com
Bits
Name
Function
On exception entry, the processor uses bit[9] of the stacked PSR to indicate the
stack alignment. On return from the exception it uses this stacked bit to restore the
correct stack alignment.
[8]
BFHFNMIGN
Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and
store instructions. This applies to the hard fault, NMI, and FAULTMASK escalated
handlers:
0 = data bus faults caused by load and store instructions cause a lock-up
1 = handlers running at priority -1 and -2 ignore data bus faults caused by load and
store instructions.
Set this bit to 1 only when the handler and its data are in absolutely safe memory.
The normal use of this bit is to probe system devices and bridges to detect control
path problems and fix them.
[7:5]
-
Reserved.
[4]
DIV_0_TRP
Enables faulting or halting when the processor executes an SDIV or UDIV
instruction with a divisor of 0:
0 = do not trap divide by 0
1 = trap divide by 0.
When this bit is set to 0,a divide by zero returns a quotient of 0.
[3]
UNALIGN_TRP
Enables unaligned access traps:
0 = do not trap unaligned halfword and word accesses1 = trap unaligned halfword
and word accesses.
If this bit is set to 1, an unaligned access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of
whether UNALIGN_TRP is set to 1.
[2]
-
Reserved.
[1]
USERSETMPEND
Enables unprivileged software access to the STIR, see Section 4.2.8 (p. 93) :
0 = disable1 = enable.
[0]
NONEBASETHRDENA
Indicates how the processor enters Thread mode:
0 = processor can enter Thread mode only when no exception is active.
1 = processor can enter Thread mode from any level under the control of an
EXC_RETURN value, see Section 2.3.7.2 (p. 27) .
4.3.9 System Handler Priority Registers
The SHPR1-SHPR3 registers set the priority level, 0 to 7 of the exception handlers that have configurable
priority.
SHPR1-SHPR3 are byte accessible. See the register summary in Table 4.12 (p. 94) for their
attributes.
The system fault handlers and the priority field and register for each handler are:
Table 4.21. System fault handler priority fields
Handler
Field
Register description
Memory management fault
PRI_4
Bus fault
PRI_5
Usage fault
PRI_6
SVCall
PRI_11
PendSV
PRI_14
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