參數(shù)資料
型號(hào)： EFM32G222F128
廠商： Energy Micro
文件頁數(shù)： 130/136頁
文件大?。?/td> 0K
描述： IC MCU 32BIT 128KB FLASH 48LQFP
特色產(chǎn)品： EFM32 Gecko
標(biāo)準(zhǔn)包裝： 1
系列： Gecko
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 32MHz
連通性： I²C，IrDA，智能卡，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 37
程序存儲(chǔ)器容量： 128KB（128K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b，D/A 1x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-TQFP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 914-1027-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
93
www.energymicro.com
byte offset 2 refers to register bits[23:16]
byte offset 3 refers to register bits[31:24].
4.2.8 Software Trigger Interrupt Register
Write to the STIR to generate a Software Generated Interrupt (SGI). See the register summary in
Table 4.2 (p. 88) for the STIR attributes.
When the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR, see
Note
Only privileged software can enable unprivileged access to the STIR.
The bit assignments are:
9
31
0
Reserved
INTID
8
Table 4.10. STIR bit assignments
Bits
Field
Function
[31:9]
-
Reserved.
[8:0]
INTID
Interrupt ID of the required SGI, in the range 0 to (n-1), where n denotes the number of interrupts given
by Table 1.1 (p. 5) . For example, a value of b000000011 specifies interrupt IRQ3.
4.2.9 Level-sensitive interrupts
All interrupt lines in the EFM32 devices are level sensitive interrupts. A level-sensitive interrupt is held
asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR
accesses the peripheral, causing it to clear the interrupt request.
When the processor enters the ISR, it automatically removes the pending state from the interrupt, see
Section 4.2.9.1 (p. 93) . If the signal is not deasserted before the processor returns from the ISR, the
interrupt becomes pending again, and the processor must execute its ISR again. This means that the
peripheral can hold the interrupt signal asserted until it no longer needs servicing.
4.2.9.1 Hardware and software control of interrupts
The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:
the NVIC detects that the interrupt signal is HIGH and the interrupt is not active
the NVIC detects a rising edge on the interrupt signal
software writes to the corresponding interrupt set-pending register bit, see Section 4.2.4 (p. 90) ,
or to the STIR to make an SGI pending, see Section 4.2.8 (p. 93) .
A pending interrupt remains pending until one of the following:
The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending
to active. Then:
When the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal
is asserted, the state of the interrupt changes to pending, which might cause the processor to
immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive.
Software writes to the corresponding interrupt clear-pending register bit.
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