參數(shù)資料
型號: EFM32G222F128
廠商: Energy Micro
文件頁數(shù): 13/136頁
文件大小: 0K
描述: IC MCU 32BIT 128KB FLASH 48LQFP
特色產(chǎn)品: EFM32 Gecko
標(biāo)準(zhǔn)包裝: 1
系列: Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 37
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 914-1027-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
11
www.energymicro.com
handlers can examine EPSR value in the stacked PSR to indicate the operation that is at fault. See
2.1.3.5.4 Interruptible-continuable instructions
When an interrupt occurs during the execution of an LDM or STM instruction, the processor:
stops the load multiple or store multiple instruction operation temporarily
stores the next register operand in the multiple operation to EPSR bits[15:12].
After servicing the interrupt, the processor:
returns to the register pointed to by bits[15:12]
resumes execution of the multiple load or store instruction.
When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.
2.1.3.5.5 If-Then block
The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in
the block is conditional. The conditions for the instructions are either all the same, or some can be the
inverse of others. See Section 3.9.3 (p. 76) for more information.
2.1.3.6 Exception mask registers
The exception mask registers disable the handling of exceptions by the processor. Disable exceptions
where they might impact on timing critical tasks.
To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to
change the value of PRIMASK or FAULTMASK. See Section 3.10.6 (p. 83), Section 3.10.7 (p. 83)
, and Section 3.10.2 (p. 80) for more information.
2.1.3.6.1 Priority Mask Register
The PRIMASK register prevents activation of all exceptions with configurable priority. See the register
summary in Table 2.2 (p. 7) for its attributes. The bit assignments are:
31
Reserved
1 0
PRIMASK
Table 2.7. PRIMASK register bit assignments
Bits
Name
Function
[31:1]
-
Reserved
[0]
PRIMASK
0 = no effect
1 = prevents the activation of all exceptions with configurable priority.
2.1.3.6.2 Fault Mask Register
The FAULTMASK register prevents activation of all exceptions except for Non-Maskable Interrupt (NMI).
See the register summary in Table 2.2 (p. 7) for its attributes. The bit assignments are:
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