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參數(shù)資料
| 型號(hào)： | EDI9LC644V |
| 英文描述： | 128Kx32 SSRAM/1Mx32 SDRAM Array(3.3V,128x32同步靜態(tài)RAM和1Mx32同步動(dòng)態(tài)RAM陣列) |
| 中文描述： | 128Kx32 SSRAM/1Mx32內(nèi)存陣列（3.3伏，128x32同步靜態(tài)內(nèi)存和1Mx32同步動(dòng)態(tài)內(nèi)存陣列） |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 460K |
| 代理商： | EDI9LC644V |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI9LC644V
EDI9LC644AV
FIG. 9 SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
CAc
CBd
CAe
RBb
CAa
RAa
CL = 2
Read
(A-Bank)
Read
(A-Bank)
Read
(B-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RAa
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0
QBd1 QAe0
QAe1
CL = 3
QAa2
QAa3
QAa0
QAa1
QAa0
QAa1
QBb0
QBb1
QBb3
QBb2
QAc0
QAc1
QBd0 QBd1
QAe0
QAe1
DON'T CARE
CBb
Note 2
Note 1
RBb
DQ
SDRAS
SDCAS
ADDR
A11 (BA)
BWE
SDA10
SDCLK
SDCE
SDWE
NOTES:
1. SDCE can be “don’t care” when SDRAS, SDCAS and SDWE are high at the clock going high edge.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| EDI9LC644V1310BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1312BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1510BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1512BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1610BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
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