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參數(shù)資料
| 型號： | EDI9LC644V |
| 英文描述： | 128Kx32 SSRAM/1Mx32 SDRAM Array(3.3V,128x32同步靜態(tài)RAM和1Mx32同步動態(tài)RAM陣列) |
| 中文描述： | 128Kx32 SSRAM/1Mx32內存陣列（3.3伏，128x32同步靜態(tài)內存和1Mx32同步動態(tài)內存陣列） |
| 文件頁數(shù)： | 20/26頁 |
| 文件大小： | 460K |
| 代理商： | EDI9LC644V |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI9LC644V
EDI9LC644AV
OUTPUT FUNCTIONAL DESCRIPTIONS
Symbol
Type
Signal
Polarity
Function
SSCLK
Input
Pulse
Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
SSADS
When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define the operation
SSOE
Input
Pulse
Active Low
to be executed by the SSRAM.
SSWE
SSCE
Input
Pulse
Active Low
SSCE disable or enable SSRAM device operation.
SDCLK
Input
Pulse
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
SDCE
Input
Pulse
Active Low
SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3.
SDRAS
When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define the operation
SDCAS
Input
Pulse
Active Low
to be executed by the SDRAM.
SDWE
Address bus for SSRAM and SDRAM
A0 and A1 are the burst address inputs for the SSRAM
During a Bank Active command cycle, A0-9, SDA10 defines the row address (RA0-10) when sampled at the
rising clock edge.
A0-16,
Input
Level
—
During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the
SDA10
rising clock edge. In addition to the row address, SDA10 is used to invoke Autoprecharge operation at the
end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and A11 defines the bank
to be precharged (low = bank A, high = bank B). If SDA10 is low, autoprecharge is disabled.
During a Precharge command cycle, SDA10 is used in conjunction with A11 to control which bank(s) to
precharge. If SDA10 is high, both bank A and Bank B will be precharged regardless of the state of A11. If
SDA10 is low, then A11 is used to define which bank to precharge.
DQ0-31
Input
Level
—
Data Input/Output are multiplexed on the same pins.
Output
BWE0-3
Input
Pulse
BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM. BWE0
is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31.
Vcc, Vss
Supply
Power and ground for the input buffers and the core logic.
VCCQ
Supply
Data base power supply pins, 3.3V (2.5V future).
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相關代理商/技術參數(shù) |
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| EDI9LC644V1310BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1312BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1510BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1512BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1610BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
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