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參數(shù)資料
| 型號： | EDI9LC644V |
| 英文描述： | 128Kx32 SSRAM/1Mx32 SDRAM Array(3.3V,128x32同步靜態(tài)RAM和1Mx32同步動態(tài)RAM陣列) |
| 中文描述： | 128Kx32 SSRAM/1Mx32內(nèi)存陣列（3.3伏，128x32同步靜態(tài)內(nèi)存和1Mx32同步動態(tài)內(nèi)存陣列） |
| 文件頁數(shù)： | 8/26頁 |
| 文件大小： | 460K |
| 代理商： | EDI9LC644V |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI9LC644V
EDI9LC644AV
FIG. 8 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
Cc0
Cd0
Ca0
Ra
CL = 2
Write
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tRCD
Ra
Qa0
tRDL
tCDL
Qa1
Qb0
Qb1
Qb2
Dc0
Dc1
Dd0
Dd1
CL = 3
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
DON'T CARE
Cb0
Note 2
Note 3
Note 1
DQ
SDRAS
SDCAS
ADDR
A11 (BA)
BWE
SDA10
SDCLK
SDCE
SDWE
NOTES:
1. To write data before burst read ends. BWE should be asserted three cycle prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written.
3. BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked
internally.
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相關(guān)代理商/技術(shù)參數(shù) |
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| EDI9LC644V1310BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1312BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1510BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1512BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1610BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
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