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參數(shù)資料
| 型號(hào)： | EDI9LC644V |
| 英文描述： | 128Kx32 SSRAM/1Mx32 SDRAM Array(3.3V,128x32同步靜態(tài)RAM和1Mx32同步動(dòng)態(tài)RAM陣列) |
| 中文描述： | 128Kx32 SSRAM/1Mx32內(nèi)存陣列（3.3伏，128x32同步靜態(tài)內(nèi)存和1Mx32同步動(dòng)態(tài)內(nèi)存陣列） |
| 文件頁數(shù)： | 25/26頁 |
| 文件大?。?/td> | 460K |
| 代理商： | EDI9LC644V |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI9LC644V
EDI9LC644AV
SDRAM AC CHARACTERISTICS
Symbol
125MHz
100MHz
83MHz
Parameter
Min
Max
Min
Max
Min
Max
Units
Clock Cycle Time (1)
CL = 3
tCC
8
1000
10
1000
12
1000
ns
CL = 2
tCC
10
1000
12
1000
15
1000
Clock to valid Output delay (1,2)
tSAC
67
8
ns
Output Data Hold Time (2)
tOH
33
3
ns
Clock HIGH Pulse Width (3)
tCH
33
3
ns
Clock LOW Pulse Width (3)
tCL
33
3
ns
Input Setup Time (3)
tSS
22
2
ns
Input Hold Time (3)
tSH
11
1
ns
CLK to Output Low-Z (2)
tSLZ
22
2
ns
CLK to Output High-Z
tSHZ
77
8
ns
Row Active to Row Active Delay (4)
tRRD
20
24
ns
RAS\ to CAS\ Delay (4)
tRCD
20
24
ns
Row Precharge Time (4)
tRP
20
24
ns
Row Active Time (4)
tRAS
50
10,000
50
10,000
60
10,000
ns
Row Cycle Time - Operation (4)
tRC
70
80
90
ns
Row Cycle Time - Auto Refresh (4,8)
tRFC
70
80
90
ns
Last Data in to New Column Address Delay (5)
tCDL
1
CLK
Last Data in to Row Precharge (5)
tRDL
1
CLK
Last Data in to Burst Stop (5)
tBDL
1
CLK
Column Address to Column Address Delay (6)
tCCD
1.5
CLK
Number of Valid Output Data (7)
2
12
1
ea
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rise time is longer than 1ns (trise/2 -0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If trise of tfall are longer than 1ns. [(trise = tfall)/2] - 1ns should be added to the parameter.
4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the
next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
8. A new command may be given tRFC after self-refresh exit.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDI9LC644V1310BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1312BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1510BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1512BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1610BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
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