參數(shù)資料
型號(hào)： EDI9LC644V
英文描述： 128Kx32 SSRAM/1Mx32 SDRAM Array(3.3V,128x32同步靜態(tài)RAM和1Mx32同步動(dòng)態(tài)RAM陣列)
中文描述： 128Kx32 SSRAM/1Mx32內(nèi)存陣列（3.3伏，128x32同步靜態(tài)內(nèi)存和1Mx32同步動(dòng)態(tài)內(nèi)存陣列）
文件頁(yè)數(shù)： 26/26頁(yè)
文件大?。?/td> 460K
代理商： EDI9LC644V
9
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI9LC644V
EDI9LC644AV
Mode Register Set
L
X
OP CODE
Auto Refresh (CBR)
L
H
X
Precharge
Single Bank
L
H
L
X
BA
L
2
Precharge all Banks
L
H
L
X
H
Bank Activate
L
H
X
BA
Row Address
2
Write
L
H
L
X
BA
L
2
Write with Auto Precharge
L
H
L
X
BA
H
2
Read
L
H
L
X
BA
L
2
Read with Auto Precharge
L
H
L
H
X
BA
H
2
Burst Termination
L
H
L
X
3
No Operation
L
H
X
Device Deselect
H
X
Data Write/Output Disable
X
L
X
4
Data Mask/Output Disable
X
H
X
4
NOTES:
1. All of the SDRAM operations are defined by states of SDCE\, SDWE\, SDRAS\, SDCAS\, and BWE0-3 at the positive rising edge of the clock.
2. Bank Select (BA), if A11 = 0 then bank A is selected, if BA = 1 then bank B is selected.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. The BWE has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE goes high at a clock timing the data outputs are disabled
and become high impedance after a two clock delay. BWE also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is
prohibited (zero clock latency).
Function
SDCE
SDRAS
SDCAS
SDWE
BWE
A11
SDA10
Notes
A9-0
SDRAM COMMAND TRUTH TABLE
CLOCK FREQUENCY AND LATENCY PARAMETERS - 125MHz SDRAM
(Unit = number of clock)
Frequency
CAS
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
70ns
50ns
20ns
10ns
125MHz (8.0ns)
3
9
6
3
2
3
1
100MHz (10.0ns)
3
7
5
2
1
83MHz (12.0ns)
2
6
4
2
1
Latency
CLOCK FREQUENCY AND LATENCY PARAMETERS - 100MHz SDRAM
(Unit = number of clock)
Frequency
CAS
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
70ns
50ns
20ns
10ns
100MHz (12.0ns)
3
7
5
2
1
83MHz (12.0ns)
2
6
5
2
1
Latency
-10
-12
Parameter
Symbol
Min
Max
Min
Max
Units
Refresh Period (1,2)
tREF
—64
—
64
ms
NOTES:
1. 4096 cycles
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device.
REFRESH CYCLE PARAMETERS
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