- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4591 > DS34T104GN+ (Maxim Integrated Products)IC TDM OVER PACKET 484TEBGA PDF資料下載
參數(shù)資料
| 型號： | DS34T104GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 329/366頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TDM OVER PACKET 484TEBGA |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 30 |
| 類型： | TDM（分時復用） |
| 應用： | 數(shù)據(jù)傳輸 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-BGA |
| 供應商設(shè)備封裝： | 484-TEBGA（23x23） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁第273頁第274頁第275頁第276頁第277頁第278頁第279頁第280頁第281頁第282頁第283頁第284頁第285頁第286頁第287頁第288頁第289頁第290頁第291頁第292頁第293頁第294頁第295頁第296頁第297頁第298頁第299頁第300頁第301頁第302頁第303頁第304頁第305頁第306頁第307頁第308頁第309頁第310頁第311頁第312頁第313頁第314頁第315頁第316頁第317頁第318頁第319頁第320頁第321頁第322頁第323頁第324頁第325頁第326頁第327頁第328頁當前第329頁第330頁第331頁第332頁第333頁第334頁第335頁第336頁第337頁第338頁第339頁第340頁第341頁第342頁第343頁第344頁第345頁第346頁第347頁第348頁第349頁第350頁第351頁第352頁第353頁第354頁第355頁第356頁第357頁第358頁第359頁第360頁第361頁第362頁第363頁第364頁第365頁第366頁
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
65 of 366
10.6.3 Clock Recovery
The TDM-over-Packet block’s innovative clock recovery process is divided into two successive phases. In the
acquisition phase, rapid frequency lock is attained. In the tracking phase, frequency lock is sustained and phase is
also tracked. During the tracking phase, jitter is attenuated to comply with the relevant telecom standards even for
packet-switched networks with relatively large packet delay variation. Packet loss immunity is also significantly
improved.
During the acquisition phase, a direct estimation of the frequency discrepancy between the far-end and near-end
service clocks continuously drives an internal frequency synthesis device through a band-limited control loop. As a
result, frequency acquisition is achieved rapidly (typically less than 10 seconds). The clock recovery capture range
is
90 ppm around the nominal service clock for any supported clock rate.
Once the frequency-monitoring unit has detected a steady frequency lock, the system switches to its tracking
phase. During the tracking phase the fill level of the received-packet jitter buffer drives the internal frequency
synthesizer through a similar band-limited control loop.
While in the tracking phase, two tasks are performed. First, the far-end service clock frequency is slowly and
accurately tracked, while compelling the regenerated near-end service clock to have jitter and wander levels that
conform to ITU-T G.823/G.824 requirements, even for networks that introduce high packet delay variation and
packet loss. This performance can be attained due to a very efficient jitter attenuation mechanism, combined with a
high resolution internal digital PLL (=0.4 ppb). Second, the received-packet jitter buffer is maintained at its fill
level, regardless of the initial frequency discrepancy between the clocks. As a result, the latency added by the
mechanism is minimized, while immunity against overflow/underflow events (caused by extreme packet delay
variation events) is substantially enhanced.
The TDM-over-Packet block supports two clock recovery modes: common clock (differential) mode and adaptive
mode.
The common clock mode is used for applications where the TDMoP gateways at both ends of the PSN path have
access to the same high-quality reference clock. This mode makes use of RTP differential mode time-stamps and
therefore the RTP header must be present in TDMoP packets when this mode is used. The common reference
clock is provided to the chip on the CLK_CMN input pin. The device is configured for common clock mode when
Clock_recovery_en=1 in
General_cfg_reg0 and RTP_timestamp_generation_mode=1 in General_cfg_reg1.
The adaptive clock mode is based solely on packet inter-arrival time and therefore can be used for applications
where a common reference clock is not available to both TDMoP gateways. This mode does not make use of time-
stamps and therefore the RTP header is not needed in the TDMoP packets when this mode is used. The device is
configured
for
adaptive
clock
mode
when
in
1
General_cfg_reg0
and
RTP_timestamp_generation_mode=0 in General_cfg_reg1.
In adaptive mode, for low-speed interfaces (up to 4.6 MHz), an on-chip digital PLL, clocked by a 38.88MHz clock
derived from the CLK_HIGH pin, synthesizes the recovered clock frequency. The frequency stability characteristics
of the CLK_HIGH signal depend on the wander requirements of the recovered TDM clock. For applications where
the recovered TDM clock must comply with G.823/G.824 requirements for traffic interfaces, typically a TCXO can
be use as the source for the CLK_HIGH signal. For applications where the recovered clock must comply with
G.823/G.824 requirements for synchronization interfaces, the CLK_HIGH signal typically must come from an
OCXO.
In addition to performing clock recovery for up to eight low-speed (typically E1/T1) signals, the device can also be
configured in a high-speed mode in which it supports one E3, T3 or STS-1 signal in and out of port 1. In high-speed
mode, the on-chip digital PLL synthesizes the recovered clock frequency divided by 10 (for STS-1) or 12 (for E3 or
T3). This clock is available on the TDM1_ACLK output pin and can be multiplied by an external PLL to get the
recovered clock of the high-speed signal (see section 15.3). High-speed mode is enabled when High_speed=1 in
2
For applications where the chip is used only for clock recovery purposes (i.e. data is not forwarded through the
chip) the external SDRAM is not needed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS34T101GN+ | IC TDM OVER PACKET 484TEBGA |
| MIC2211-GOYML TR | IC REG LDO 1.8V/2.9V 10-MLF |
| MIC2211-GJYML TR | IC REG LDO 1.8V/2.5V 10-MLF |
| MIC2211-SGYML TR | IC REG LDO 3.3V/1.8V 10-MLF |
| MIC2211-GPYML TR | IC REG LDO 1.8V/3V 10-MLF |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS34T104GN+ | 功能描述:通信集成電路 - 若干 Quad TDM Over Packet Chip RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T108 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T108DK-L1 | 功能描述:以太網(wǎng)開發(fā)工具 RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
發(fā)布緊急采購，3分鐘左右您將得到回復。