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參數(shù)資料
| 型號(hào)： | DS34T104GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 23/366頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TDM OVER PACKET 484TEBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 類(lèi)型： | TDM（分時(shí)復(fù)用） |
| 應(yīng)用： | 數(shù)據(jù)傳輸 |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-TEBGA（23x23） |
| 包裝： | 托盤(pán) |
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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
119 of 366
Table 10-43. Registers Related to T1 Receive BOC
Register Name
Description
Functions
Page
Receive BOC Control Register
reset and filter/disintegration settings
Receive Bit Oriented Code Register
received BOC message
Receive Latched Status Register 7
BOC detected, cleared latched status
Receive Interrupt Mask Register 7
interrupt mask bits
In T1 ESF mode, the receive framer continuously monitors the FDL bits for a valid BOC message. The BOC detect
status bit RLS7-T1.BD is set after a valid message has been detected for a time specified by the receive BOC filter
bits RBOCC.RBF[1:0]. The 6-bit BOC message is then available to be read from the RBOC register. After the CPU
clears the BD bit, it remain clears until a new BOC is detected (or the same BOC is detected following a BOC clear
event). The BOC clear status bit RLS7-T1.BC is set when a valid BOC is no longer being detected for a time
specified by the receive BOC disintegration bits RBOCC.RBD[1:0]. The BD and BC status bits can cause an
interrupt request if enabled by the associated interrupt mask bits in the RIM7-T1 register.
10.11.4.3 Legacy T1 Transmit FDL
Note: For most applications, BOC controllers or HDLC controllers in the framer and formatter are better tools for
communication over the FDL than the TFDL and RFDL registers. The registers related to transmitting over the FDL
using the TFDL register are listed in the table below.
Table 10-44. Registers Related to Legacy T1 Transmit FDL
Register Name
Description
Functions
Page
Transmit FDL Register
8 bits of FDL data to transmit
Transmit Control Register 2
source of Tx FDL bits
Transmit Latched Status Register 2
transmit FDL empty bit (TFDLE)
Transmit Interrupt Mask Register 2
interrupt mask bit for TFDLE bit
When enabled with TCR2-T1.TFDLS=0, the transmit formatter sources the FDL (in the ESF framing mode) or the
Fs bits (in the SF framing mode) from the transmit FDL register (TFDL). The LSb is transmitted first. After all eight
bits have been shifted out of TFDL, the formatter sets TLS2.TFDLE=1 to inform the CPU that the buffer is empty
and that more data is needed. TFDLE can cause an interrupt request if enabled by the corresponding interrupt
mask bit in TIM2. The CPU has 2ms (8 * 2 * 125
s) to update TFDL with a new value. If it is not updated, the old
value is transmitted again. Note that in this mode, no zero stuffing is applied to the FDL data. It is strongly
suggested that the HDLC controller be used for FDL messaging applications.
In the SF framing mode, the formatter sources the Fs framing pattern from the lower six bits of the TFDL register,
and TLS2.TFDLE is set every 1.5ms (12 * 125
s). For the standard framing pattern, TFDL must be set to 0x1C and
TCR2-T1.TFDLS should be set to zero.
10.11.4.4 Legacy T1 Receive FDL
Note: For most applications, BOC controllers or HDLC controllers in the framer and formatter are better tools for
communication over the FDL than the TFDL and RFDL registers. The registers related to receiving data from the
FDL using the RFDL register are listed in the table below.
Table 10-45. Registers Related to Legacy T1 Receive FDL
Register Name
Description
Functions
Page
Receive FDL Register
8 bits of received FDL data
Receive Latched Status Register 7
receive FDL full bit (TFDLF)
Receive Interrupt Mask Register 7
interrupt mask bit for RFDLF bit
In the receive section, the recovered FDL bits or Fs bits are always shifted one-by-one into the receive FDL register
(RFDL). The LSb is the first bit received. Since RFDL is 8 bits in length, it fills up every 2ms (8 * 2 * 125
s). After
all eight bits have been shifted into RFDL, the framer sets RLS7-T1.RFDLF=1 to inform the CPU that the buffer is
full and needs to be read. RFDLF can cause an interrupt request if enabled by the corresponding interrupt mask bit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS34T101GN+ | IC TDM OVER PACKET 484TEBGA |
| MIC2211-GOYML TR | IC REG LDO 1.8V/2.9V 10-MLF |
| MIC2211-GJYML TR | IC REG LDO 1.8V/2.5V 10-MLF |
| MIC2211-SGYML TR | IC REG LDO 3.3V/1.8V 10-MLF |
| MIC2211-GPYML TR | IC REG LDO 1.8V/3V 10-MLF |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS34T104GN+ | 功能描述:通信集成電路 - 若干 Quad TDM Over Packet Chip RoHS:否 制造商:Maxim Integrated 類(lèi)型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T108 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T108DK-L1 | 功能描述:以太網(wǎng)開(kāi)發(fā)工具 RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類(lèi)型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類(lèi)型:RMII 工作電源電壓: |
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