參數(shù)資料
型號： DS32506N#
廠商： Maxim Integrated Products
文件頁數(shù)： 88/130頁
文件大小： 0K
描述： IC LIU DS3/E3/STS-1 484-BGA
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 60
類型： 線路接口裝置（LIU）
規(guī)程： IEEE 1149.1
電源電壓： 1.8V, 3.3V
安裝類型： 表面貼裝
封裝/外殼： 484-BGA
供應商設備封裝： 484-BGA（23x23）
包裝： 管件
DS32506/DS32508/DS32512
60 of 130
Register Name:
GLOBAL.SR
Register Description:
Global Status Register
Register Address:
028h
Bit #
15
14
13
12
11
10
9
8
Name
—
Default
—
Bit #
7
6
5
4
3
2
1
0
Name
—
CLOL
—
GPMS
Default
—
0
—
0
Bit 2: CLAD Loss of Lock (CLOL).
This bit is set when the CLAD is not locked to the reference frequency.
Bit 0: Global Performance Monitoring Update Status (GPMS).
This bit is set when the PORT.SR:PMS status
bits are set in all of the ports that are enabled for global update control (i.e., all ports that have PORT.CR1:PMUM =
1). Ports that have PORT.CR1:PMUM = 0 have no effect on this bit. In global software update mode, the global
update request bit (GLOBAL.CR1:GPMU) should be held high until this status bit goes high. See Section 8.7.4.
0 = The associated update request signal is low or not all register updates are completed.
1 = The requested performance register updates are all completed.
Register Name:
GLOBAL.SRL
Register Description:
Global Status Register Latched
Register Address:
02Ah
Bit #
15
14
13
12
11
10
9
8
Name
—
Bit #
7
6
5
4
3
2
1
0
Name
—
CLKCL
CLKBL
CLKAL
CLADL
CLOLL
G1SREFL
GPMSL
Bit 6: CLAD C Clock Activity Latched (CLKCL).
This bit is set when the signal on the CLKC pin is active. Note:
This bit should always be low when GLOBAL.CR2:CLAD[6:4]
≠ 000. See Section 8.7.1.
Bit 5: CLAD B Clock Activity Latched (CLKBL).
This bit is set when the signal on the CLKB pin is active. Note:
This bit should always be low when GLOBAL.CR2:CLAD[6:4]
≠ 000. See Section 8.7.1.
Bit 4: CLAD A Clock Activity Latched (CLKAL).
This bit is set when the signal on the CLKA pin is active. Note:
This bit should always be low when GLOBAL.CR2:CLAD[6:4]
≠ 000. See Section 8.7.1.
Bit 3: CLAD Reference Clock Activity Status Latched (CLADL).
This bit is set when the CLAD PLL reference
clock signal on the REFCLK pin is active. Note: When GLOBAL.CR2:CLAD[6:4] = 000, the REFCLK pin is unused.
See Section 8.7.1.
Bit 2: CLAD Loss of Lock Latched (CLOLL).
This bit is set when the GLOBAL.SR:CLOL status bit transitions
from low to high.
Bit 1: Global One-Second Status Latched (G1SREFL).
This bit is set once each second when the internal global
one-second timer signal transitions low to high. When set, this bit causes an interrupt if interrupt enables
GLOBAL.SRIE:G1SREFIE and GLOBAL.ISRIE:GSRIE are both set. See Section 8.7.1.
Bit 0: Global Performance Monitoring Update Status Latched (GPMSL).
This bit is set when the
GLOBAL.SR:GPMS status bit changes from low to high. When set, this bit causes an interrupt if interrupt enables
GLOBAL.SRIE:GPMSIE and GLOBAL.ISRIE:GSRIE are both set. See Section 8.7.1.
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DS32506N# 功能描述:網(wǎng)絡控制器與處理器 IC 6-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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DS32506W 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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