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| 型號(hào)： | DS32506N# |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 69/130頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU DS3/E3/STS-1 484-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | IEEE 1149.1 |
| 電源電壓： | 1.8V, 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-BGA（23x23） |
| 包裝： | 管件 |
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goes low. The PMS has an associated latched status bit that can generate an interrupt if enabled. The port PMS
signal does not go high until an update of all the appropriately configured block-level performance monitoring
counters in the port has been completed. The global PMS signal does not go high until an update of all the
appropriately configured port-level performance monitoring counters in the entire chip has been completed.
8.7.5 Transmit Manual Error Insertion
Various types of errors can be inserted in the transmit data stream using the Transmit Manual Error Insertion
(TMEI) signal, which can be sourced from a block-level register bit, a port register bit (PORT.CR1:TMEI), a global
register bit (GLOBAL.CR1:TMEI), or a general-purpose I/O pin (GPIOB2). To use GPIOB2 as the TMEI signal,
GLOBAL.CR1.MEIMS is set to 1, the appropriate PORT.CR1.MEIMS bits are set to 1, and the appropriate block-
level MEIMS bits are set to 1. To use the global TMEI register bit, GLOBAL.CR1.MEIMS is set to 0, the appropriate
PORT.CR1.MEIMS bits are set to 1, and the appropriate block-level MEIMS bits are set to 1. To use the port TMEI
register bit, the associated PORT.CR1.MEIMS is set to 0 and the appropriate block-level MEIMS bits are set to 1.
To use the block-level TSEI register bit, the associated block-level MEIMS bit is set to 0.
In order for an error of a particular type to be inserted, the error type must be enabled by setting the associated
error insertion enable bit in the associated block's error insertion register. Once enabled, a single error is inserted
at the next opportunity when the TMEI signal transitions from zero to one. Note: If the TMEI signal has multiple
zero-to-one transitions between error insertion opportunities, only a single error is inserted.
8.8 8-/16-Bit Parallel Microprocessor Interface
See Table 11-8 and Figure 11-3 to Figure 11-10 for parallel interface timing diagrams and parameters.
8.8.1 8-Bit and 16-Bit Bus Widths
When the IFSEL pins are set to 1XX, the device presents a parallel microprocessor interface. In 8-bit modes
(IFSEL = 10X), the address is composed of all the address bits including A[0], the lower 8 data lines D[7:0] are
used, and the upper 8 data lines D[15:8] are disabled (high impedance). In 16-bit modes (IFSEL = 11X), the
8.8.2 Byte Swap Mode
In 16-bit modes (IFSEL = 11X), the microprocessor interface can operate in byte swap mode. The BSWAP pin is
used to determine whether byte swapping is enabled. This pin should be static and not change during operation.
When the BSWAP pin is low the upper register bits REG[15:8] are mapped to the upper external data bus lines
D[15:8], and the lower register bits REG[7:0] are mapped to the lower external data bus lines D[7:0]. When the
BSWAP pin is high the upper register bits REG[15:8] are mapped to the lower external data bus lines D[7:0], and
the lower register bits REG[7:0] are mapped to the upper external data bus lines D[15:8].
8.8.3 Read-Write And Data Strobe Modes
The processor interface can operate in either read-write strobe mode (also known as "Intel" mode) or data strobe
mode (also known as "Motorola" mode). When IFSEL = 1X0 the read-write strobe mode is enabled. In this mode a
negative pulse on
When IFSEL = 1X1 the data strobe mode is enabled. In this mode, a negative pulse on DS when R/W is high
performs a read cycle, and a negative pulse on
8.8.4 Multiplexed and Nonmultiplexed Operation
In all parallel interface modes the interface supports both multiplexed and nonmultiplexed operation. For
multiplexed operation in 8-bit modes, wire A[10:8] to the processor’s A[10:8] pins, wire A[7:0] to D[7:0] and to the
processor’s multiplexed address/data bus, and connect the ALE pin to the appropriate pin on the processor. For
nonmultiplexed 8-bit operation, wire ALE high and wire A[10:0] and D[7:0] to the appropriate pins on the processor.
For multiplexed operation in 16-bit modes, wire A[10:0] to D[10:0], wire D[15:0] to the CPU’s multiplexed
address/data bus, and connect the ALE pin to the appropriate pin on the processor. For nonmultiplexed 16-bit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS32506N# | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 6-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32506N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 6-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32506NA2 | 制造商:Maxim Integrated Products 功能描述:DS32506A2 X6 DS3/E3 LIU - Rail/Tube |
| DS32506NW | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32506W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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