12.2 Alternate Sa/Si Bit Access Based on Double-Frame On the receive side, the RAF and RNAF regis" />
參數資料
型號： DS26502LN+
廠商： Maxim Integrated Products
文件頁數： 98/125頁
文件大?。?/td> 0K
描述： IC T1/E1/J1 64KCC ELEMENT 64LQFP
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 160
類型： BITS 元件，多路復用器
PLL： 是
主要目的： T1/E1
輸入： 時鐘
輸出： 時鐘
電路數： 1
比率 - 輸入:輸出： 2:3
差分 - 輸入:輸出： 無/無
頻率 - 最大： 6.312MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應商設備封裝： 64-LQFP（10x10）
包裝： 托盤
產品目錄頁面： 1430 (CN2011-ZH PDF)
DS26502 T1/E1/J1/64KCC BITS Element
74 of 125
12.2 Alternate Sa/Si Bit Access Based on Double-Frame
On the receive side, the RAF and RNAF registers will always report the data as it received in the Sa and
Si bit locations. The RAF and RNAF registers are updated on align frame boundaries. The setting of the
receive align frame bit in status register 4 (SR4.0) will indicate that the contents of the RAF and RNAF
have been updated. The host can use the SR4.0 bit to know when to read the RAF and RNAF registers.
The host has 250
s to retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the transmit
align frame bit in status register 4 (SR4.3). The host can use the SR4.3 bit to know when to update the
TAF and TNAF registers. It has 250
s to update the data or else the old data will be retransmitted. If the
TAF an TNAF registers are only being used to source the align frame and non-align frame-sync
patterns, then the host need only write once to these registers. Data for the Si bit can come from the Si
bits of the RAF and TNAF registers, the TSiAF and TSiNAF registers, or passed through from the TSER
pin.
Register Name:
RAF
Register Description:
Receive Align Frame Register
Register Address:
56h
Bit #
7
6
5
4
3
2
1
0
Name
Si
FAS6
FAS5
FAS4
FAS3
FAS2
FAS1
FAS0
Default
0
HW
Mode
X
Bit 0: Frame Alignment Signal Bit 0 (FAS0). In normal operation this bit will be = 1.
Bit 1: Frame Alignment Signal Bit 1 (FAS1). In normal operation this bit will be = 1.
Bit 2: Frame Alignment Signal Bit 2 (FAS2). In normal operation this bit will be = 0.
Bit 3: Frame Alignment Signal Bit 3 (FAS3). In normal operation this bit will be = 1.
Bit 4: Frame Alignment Signal Bit 4 (FAS4). In normal operation this bit will be = 1.
Bit 5: Frame Alignment Signal Bit 5 (FAS5). In normal operation this bit will be = 0.
Bit 6: Frame Alignment Signal Bit 6 (FAS6). In normal operation this bit will be = 0.
Bit 7: International Bit (Si)
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相關代理商/技術參數
參數描述
DS26502LN+ 功能描述:計時器和支持產品 E1/T1/J1/64Kcc Bits Element RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內部定時器數量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel
DS26503 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:T1/E1/J1/64KCC BITS Element
DS26503_07 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:T1/E1/J1 BITS Element
DS26503DK 功能描述:時鐘和定時器開發(fā)工具 DS26503 Dev Kit RoHS:否 制造商:Texas Instruments 產品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
DS26503L 功能描述:計時器和支持產品 E1-T1-J1 Bits Element RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內部定時器數量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel
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