參數(shù)資料
型號: DS26502LN+
廠商: Maxim Integrated Products
文件頁數(shù): 68/125頁
文件大?。?/td> 0K
描述: IC T1/E1/J1 64KCC ELEMENT 64LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 160
類型: BITS 元件,多路復(fù)用器
PLL:
主要目的: T1/E1
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:3
差分 - 輸入:輸出: 無/無
頻率 - 最大: 6.312MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS26502 T1/E1/J1/64KCC BITS Element
47 of 125
Table 9-1. E1 Sync/Resync Criteria
FRAME OR
MULTIFRAME
LEVEL
SYNC CRITERIA
RESYNC CRITERIA
ITU SPEC.
FAS
FAS present in frame N and
N + 2, and FAS not present in
frame N + 1
Three consecutive incorrect FAS
received
Alternate: (E1RCR.2 = 1) The above
criteria is met or three consecutive
incorrect bit 2 of non-FAS received
G.706
4.1.1
4.1.2
CRC4
Two valid MF alignment
words found within 8ms
915 or more CRC4 code words out of
1000 received in error
G.706
4.2 and 4.3.2
CAS
Valid MF alignment word
found and previous time slot
16 contains code other than
all zeros
Two consecutive MF alignment
words received in error
G.732 5.2
Register Name:
E1TCR
Register Description:
E1 Transmit Control Register
Register Address:
1Eh
Bit #
7
6
5
4
3
2
1
0
Name
TFPT
TSiS
THDB3
Default
0
HW
Mode
0
HBE
PIN 55
0
Bits 0, 2, 3, 5, 6:Unused, must be set = 0 for proper operation.
Bit 1: Transmit HDB3 Enable (THDB3)
0 = HDB3 disabled
1 = HDB3 enabled
Bit 4: Transmit International Bit Select (TSiS)
0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (in this mode, E1TCR1.7 must be set to 0)
Bit 7: Transmit Time Slot 0 Pass-Through (TFPT)
0 = FAS bits/Sa bits/remote alarm sourced internally from the TAF and TNAF registers
1 = FAS bits/Sa bits/remote alarm sourced from TSER
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