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參數(shù)資料
| 型號(hào)： | DS26502LN+ |
| 廠(chǎng)商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 105/125頁(yè) |
| 文件大小： | 0K |
| 描述： | IC T1/E1/J1 64KCC ELEMENT 64LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類(lèi)型： | BITS 元件，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | T1/E1 |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:3 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 6.312MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 1430 (CN2011-ZH PDF) |
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DS26502
80 of 125
The transmit line drive has two modes of operation: fixed gain or automatic gain. In the fixed gain mode,
the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude. In the
automatic gain mode, the transmitter adjusts its output level to compensate for slight variances in the
network load. See the Transmit Line Build-Out Control (TLBC) register for details.
13.3.1 Transmit Short-Circuit Detector/Limiter
The DS26502 has an automatic short-circuit limiter that limits the source current to approximately 50mA
(rms) on the network side of the transformer in E1 modes of operations and 70mA (RMS) on the network
side of the transformer in T1 modes of operation. These values are approximate and are not guaranteed by
production testing. This feature can be disabled by setting the SCLD bit (LIC2.1) = 1. TCLE (SR1.2)
provides a real-time indication of when the current limiter is activated. If the current limiter is disabled,
TCLE will indicate that a short-circuit condition exist. Status Register SR1.2 provides a latched version
of the information, which can be used to activate an interrupt when enable via the IMR1 register. When
set low, the TPD bit (LIC1.0) will power-down the transmit line driver and three-state the TTIP and
TRING pins.
13.3.2 Transmit Open-Circuit Detector
The DS26502 can also detect when the TTIP or TRING outputs are open circuited. TOCD (SR1.1) will
provide a real-time indication of when an open circuit is detected. SR1 provides a latched version of the
information (SR1.1), which can be used to activate an interrupt when enable via the IMR1 register. The
functionality of these bits is not guaranteed by production testing.
13.3.3 Transmit BPV Error Insertion
When IBPV (LIC2.5) is transitioned from a zero to a one, the device waits for the next occurrence of
three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error
insertion.
13.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode)
The DS26502 can transmit the 2.048MHz square-wave synchronization clock. To transmit the 2.048MHz
clock, when in E1 mode, set the mode configuration bits in the Mode Configuration Register (MCREG).
13.4 MCLK Pre-Scaler
A 2.048MHz x 2
N (where N = 0 to 3), 1.544MHz x 2N (where N = 0 to 3), or 12.8MHz (available in CPU
interface mode only) clock must be applied to MCLK. A pre-scaler (divide by 2, 4, or 8) and PLLs are
selected to product an internal 2.048MHz or 1.544MHz clock. ITU specification G.703 requires an accuracy
of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces.
A pre-scaler divides the 16.384MHz, 12.8MHz, 8.192MHz, or 4.096MHz clock down to 2.048MHz. An on-
board PLL for the jitter attenuator converts the 2.048MHz clock to a 1.544MHz rate for T1 applications.
Setting JACKS0 (LIC2.3) to logic 0 bypasses this PLL.
13.5 Jitter Attenuator
The jitter attenuator is only available in T1 and E1 modes. The DS26502’s jitter attenuator can be set to a
depth of either 32 bits or 128 bits via the JABDS bit (LIC1.2). The 128-bit mode is used in applications
where large excursions of wander are expected. The 32-bit mode is used in delay-sensitive applications.
The characteristics of the attenuation are shown in Figure 13-10 and Figure 13-11. The jitter attenuator
can be placed in either the receive path or the transmit path by appropriately setting or clearing the JAS
bit (LIC1.3). If the part is configured for hardware mode and the jitter attenuator is enabled, it will
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26502LN+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 E1/T1/J1/64Kcc Bits Element RoHS:否 制造商:Micrel 類(lèi)型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| DS26503 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:T1/E1/J1/64KCC BITS Element |
| DS26503_07 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:T1/E1/J1 BITS Element |
| DS26503DK | 功能描述:時(shí)鐘和定時(shí)器開(kāi)發(fā)工具 DS26503 Dev Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類(lèi)型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| DS26503L | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 E1-T1-J1 Bits Element RoHS:否 制造商:Micrel 類(lèi)型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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