參數(shù)資料
型號(hào): DS26502LN+
廠商: Maxim Integrated Products
文件頁數(shù): 87/125頁
文件大?。?/td> 0K
描述: IC T1/E1/J1 64KCC ELEMENT 64LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: BITS 元件,多路復(fù)用器
PLL:
主要目的: T1/E1
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:3
差分 - 輸入:輸出: 無/無
頻率 - 最大: 6.312MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS26502 T1/E1/J1/64KCC BITS Element
64 of 125
12. E1 SYNCHRONIZATION STATUS MESSAGE
The DS26502 provides access to both the transmit and receive Sa/Si bits. In E1, the Sa bits are used to
transmit and receive the SSM. The primary method to access the Sa (and Si) bits is based on CRC4
multiframe access. An alternate method is based on double-frame access.
Table 12-1. E1 SSM Messages
QUALITY
LEVEL
DESCRIPTION
Sa BIT
MESSAGE
0
Quality unknown (existing sync network)
0000
1
Reserved
0001
2
Rec. G.811 (Traceable to PRS)
0010
3
Reserved
0011
4
SSU-A (Traceable to SSU type A, see G.812)
0100
5
Reserved
0101
6
Reserved
0110
7
Reserved
0111
8
SSU-B (Traceable to SSU type B, see G.812)
1000
9
Reserved
1001
10
Reserved
1010
11
Synchronous Equipment Timing Source
1011
12
Reserved
1100
13
Reserved
1101
14
Reserved
1110
15
Do not use for synchronization
01111
In E1 operation, SSMs are transmitted using one of the Sa bits—Sa4, Sa5, Sa6, Sa7, or Sa8. The SSM is
transmitted MSB first in the first frame of the multiframe. Each multiframe will contain two SSMs, one in
each sub-multiframe. An SSM is declared valid when the message in three sub-multiframes are alike.
12.1 Sa/Si Bit Access Based on CRC4 Multiframe
On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the
Si and Sa bits as they are received. These registers are updated on CRC4 multiframes. A bit in status
register 4 (SR4.1) indicates the multiframe boundary. The host can use the SR4.1 bit to know when to
read these registers. The user has 2ms to retrieve the data before it is lost. The MSB of each register is the
first received. See the following register descriptions for more details.
On the transmit side, there is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4 to TSa8) that, via
the transmit Sa bit control register (TSaCR), can be programmed to insert both Si and Sa data. Data is
sampled from these registers with the setting of the transmit multiframe bit in status register 2 (SR4.4).
The host can use the SR4.4 bit to know when to update these registers. It has 2ms to update the data or
else the old data will be retransmitted. The MSB of each register is the first bit transmitted. See the
following register descriptions for details.
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