參數(shù)資料
型號(hào): DS26502LN+
廠商: Maxim Integrated Products
文件頁數(shù): 67/125頁
文件大小: 0K
描述: IC T1/E1/J1 64KCC ELEMENT 64LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: BITS 元件,多路復(fù)用器
PLL:
主要目的: T1/E1
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:3
差分 - 輸入:輸出: 無/無
頻率 - 最大: 6.312MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS26502 T1/E1/J1/64KCC BITS Element
46 of 125
9. E1 FRAMER/FORMATTER CONTROL REGISTERS
The E1 framer portion of the DS26502 is configured via a set of two control registers. Typically, the
control registers are only accessed when the system is first powered up. Once the DS26502 has been
initialized, the control registers will only need to be accessed when there is a change in the system
configuration. There is one receive control register (E1RCR) and one transmit control register (E1TCR).
There are also two information registers and a status register, as well as an interrupt mask register. Each
of these registers is described in this section.
9.1 E1 Control Registers
Register Name:
E1RCR
Register Description:
E1 Receive Control Register
Register Address:
1Dh
Bit #
7
6
5
4
3
2
1
0
Name
RLOSA
RHDB3
FRC
SYNCE
RESYNC
Default
0
HW
Mode
0
HBE
PIN 55
0
Bit 0: Resync (RESYNC). When toggled from low to high, a resync is initiated. Must be cleared and set again for a
subsequent resync.
Bit 1: Sync Enable (SYNCE)
0 = auto resync enabled
1 = auto resync disabled
Bit 2: Frame Resync Criteria (FRC)
0 = resync if FAS received in error three consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times
Bits 3, 4, 7: Unused, must be set = 0 for proper operation.
Bit 5: Receive HDB3 Enable (RHDB3)
0 = HDB3 disabled
1 = HDB3 enabled
Bit 6: Receive Loss Of Signal (RLOS) Alternate Criteria (RLOSA). Defines the criteria for a Receive Loss Of Signal
condition.
0 = RLOS declared upon 255 consecutive zeros (125s)
1 = RLOS declared upon 2048 consecutive zeros (1ms)
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